Xin Chen

Orcid: 0000-0003-2706-5069

Affiliations:
  • Nanjing University of Aeronautics and Astronautics, China


According to our database1, Xin Chen authored at least 32 papers between 2008 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2025
FPGA-Based Implementation and Quantization of Convolutional Neural Networks.
Proceedings of the 2025 3rd International Conference on Communication Networks and Machine Learning, 2025

2024
Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Application.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2024

Double-Node-Upset Self-Recoverable Latch Design for Wide Voltage Range Application.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

2023
Trade-off Mechanism Between Reliability and Performance for Data-flow Soft Error Detection.
J. Electron. Test., December, 2023

FPGA Design of Blind Zone-Suppressed Phase Frequency Detector via Reset Mask and Edge Recovery Operations.
Circuits Syst. Signal Process., August, 2023

Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2023

Spotlight: An Impairing Packet Transmission Attack Targeting Specific Node in NoC-based TCMP.
Proceedings of the IEEE European Test Symposium, 2023

FPGA-Based Cross-Hardware MBU Emulation Platform for Layout-Level Digital VLSI.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023

2022
Hybrid multi-level hardware Trojan detection platform for gate-level netlists based on XGBoost.
IET Comput. Digit. Tech., 2022

Blinding HT: Hiding Hardware Trojan signals traced across multiple sequential levels.
IET Circuits Devices Syst., 2022

PUF-based Secure Test Wrapper Design for Network-on-Chip.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

2021
Z-domain modeling methodology for homodyne digital optical phase-locked loop.
IEICE Electron. Express, 2021

Efficient Anti-Glare Ceramic Decals Defect Detection by Incorporating Homomorphic Filtering.
Comput. Syst. Sci. Eng., 2021

Hardware Trojans Detection Through RTL Features Extraction and Machine Learning.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021

2020
A New Hardware Trojan Design: Distinguishing Between Trigger Inputs and Functional Inputs Is Difficult: Work-in-Progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2020

2019
Small Area High Speed Configurable FFT Processor.
Proceedings of the International Conference on IC Design and Technology, 2019

2018
VLSI design of low-cost and high-precision fixed-point reconfigurable FFT processors.
IET Comput. Digit. Tech., 2018

2017
FPGA based highly efficient MISTY1 architecture.
IEICE Electron. Express, 2017

2016
A Modified Partial Product Generator for Redundant Binary Multipliers.
IEEE Trans. Computers, 2016

A scalable multi-pipeline JPEG encoding architecture.
Proceedings of the 28th International Conference on Microelectronics, 2016

2014
Built-in self test design of power switch with clock-gated charge/discharge transistor.
IET Comput. Digit. Tech., 2014

An optimized delay-aware common subexpression elimination algorithm for hardware implementation of binary-field linear transform.
IEICE Electron. Express, 2014

A New Redundant Binary Partial Product Generator for Fast 2n-Bit Multiplier Design.
Proceedings of the 17th IEEE International Conference on Computational Science and Engineering, 2014

2013
Evaluation of Correlation Power Analysis Resistance and Its Application on Asymmetric Mask Protected Data Encryption Standard Hardware.
IEEE Trans. Instrum. Meas., 2013

A Design Methodology for Three-Dimensional Hybrid NoC-Bus Architecture.
IEICE Trans. Electron., 2013

BIST design of power switch.
IEICE Electron. Express, 2013

2011
A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Novel Combined Proportional-Derivative Control for Electrostatic MEMS Mirror Actuation.
IEICE Trans. Electron., 2011

2010
Dynamic Voltage Scaling for Real-Time Systems with System Workload Analysis.
IEICE Trans. Electron., 2010

2009
A Harmonic-Free All Digital Delay-Locked Loop Using an Improved Fast-Locking Successive Approximation Register-Controlled Scheme.
IEICE Trans. Electron., 2009

Analysis of Jitter in CMOS Ring Oscillators due to Power Supply Noise.
IEICE Trans. Electron., 2009

2008
A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop.
IEICE Trans. Electron., 2008


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