Na Bai

Orcid: 0000-0001-9596-8142

According to our database1, Na Bai authored at least 36 papers between 2012 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
A Low-Cost Input-Split Inverter-Based Triple-Node-Upset Recoverable Latch Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2026

Low-Delay, High-Robustness DNU Self-Healing Latch Based on the C-Element Feedback Loop.
IEEE Trans. Aerosp. Electron. Syst., 2026

A Highly Robust and Low-Cost Multiple Node Upset Resilient Fast Latch for Radiation Applications.
IEEE Trans. Aerosp. Electron. Syst., 2026

2025
TUTPFL: Triple Node Upset-Tolerant and Single-Event Transient-Filtered Low-Power Latch With HSPICE and FPGA-Based Verifications.
IEEE Trans. Very Large Scale Integr. Syst., October, 2025

A High-Performance Low-Power Double-Node Upset Resilient Latch for Harsh Radiation Environments.
IEEE Trans. Very Large Scale Integr. Syst., September, 2025

Reconfigurable Radiation-Hardened SRAM Cell Design for Different Radiation Environments.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2025

Triple-Node-Upset Recovery High-Impedance-State-Insensitive and Single-Event-Transient Filtering Latch for Aerospace Applications.
IEEE Trans. Aerosp. Electron. Syst., August, 2025

Design of Nonvolatile and Multinode-Upset Recoverable Latches Based on Magnetic Tunnel Junction and CMOS.
IEEE Trans. Very Large Scale Integr. Syst., July, 2025

Cost-Optimized Double-Node-Upset-Recovery Latch Designs With Aging Mitigation and Algorithm-Based Verification for Long-Term Robustness Enhancement.
IEEE Trans. Very Large Scale Integr. Syst., June, 2025

Low-iteration hybrid computing CORDIC architecture.
Microelectron. J., 2025

An enhanced interlocked feedback structure-based dual-node upset resilient latch.
Microelectron. J., 2025

Multi-Task Graph Attention Net for Electricity Consumption Prediction and Anomaly Detection.
Comput., 2025

Abuttable Analog Cell Library and Automatic AMS Layout.
Proceedings of the 2025 International Symposium on Physical Design, 2025

APCer: An Agile Physical Compiler for Multi-Port Register File.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Radiation-Resistant ZnO Thin-Film Transistor Voltage Reference.
Proceedings of the 34th IEEE Asian Test Symposium, 2025

2024
A 14T radiation hardened SRAM for space applications with high reliability.
Int. J. Circuit Theory Appl., June, 2024

Soft-Error-Aware SRAM With Multinode Upset Tolerance for Aerospace Applications.
IEEE Trans. Very Large Scale Integr. Syst., January, 2024

A low dropout regulator design with 20.4 μA quiescent current and high power supply rejection.
Integr., 2024

AMSNet: Netlist Dataset for AMS Circuits.
CoRR, 2024

Deep Learning Methods With the Improved Attention for Explainable Image Recognition.
IEEE Access, 2024

A Low-Energy Critical Charge-Enhanced SRAM for Aerospace Applications.
Proceedings of the IEEE International Test Conference in Asia, 2024

2023
Design of SEU and DNU-resistant SRAM cells based on polarity reinforcement feature.
Int. J. Circuit Theory Appl., October, 2023

A multi-task attention tree neural net for stance classification and rumor veracity detection.
Appl. Intell., May, 2023

JUTAR: Joint User-Association, Task-Partition, and Resource-Allocation Algorithm for MEC Networks.
Sensors, February, 2023

Highly stable soft-error immune SRAM with multi-node upset recovery for aerospace applications.
Integr., 2023

2022
An interpretable deep learning workflow for discovering subvisual abnormalities in CT scans of COVID-19 inpatients and survivors.
Nat. Mach. Intell., 2022

Naive Bayes classifier based on memristor nonlinear conductance.
Microelectron. J., 2022

Rumor detection based on a Source-Replies conversation Tree Convolutional Neural Net.
Computing, 2022

Logic Design and Power Optimization of Floating-Point Multipliers.
Comput. Intell. Neurosci., 2022

2021
A Design of a Developable Automatic Avoidance System of UAV Based on ADS-B.
Wirel. Commun. Mob. Comput., 2021

Rumour Detection Based on Graph Convolutional Neural Net.
IEEE Access, 2021

2020
A Stochastic Attention CNN Model for Rumor Stance Classification.
IEEE Access, 2020

2014
A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for Reducing Timing Variation of SRAM Sense Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Built-in self test design of power switch with clock-gated charge/discharge transistor.
IET Comput. Digit. Tech., 2014

2013
A low active and leakage power SRAM using a read and write divided and BIST programmable timing control circuit.
Microelectron. J., 2013

2012
Bitline Leakage Current Compensation Circuit for High-Performance SRAM Design.
Proceedings of the Seventh IEEE International Conference on Networking, 2012


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