Xin Zhao

Orcid: 0000-0003-4623-9829

According to our database1, Xin Zhao authored at least 20 papers between 2016 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2025
Trident: The Acceleration Architecture for High-Performance Private Set Intersection.
IEEE Trans. Computers, April, 2025

PIPECIM: Energy-Efficient Pipelined Computing-in-Memory Computation Engine With Sparsity-Aware Technique.
IEEE Trans. Very Large Scale Integr. Syst., February, 2025

2024
SuperHCA: An Efficient Deep-Learning Edge Super-Resolution Accelerator With Sparsity-Aware Heterogeneous Core Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024

General Purpose Deep Learning Accelerator Based on Bit Interleaving.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024

HDSuper: High-Quality and High Computational Utilization Edge Super-Resolution Accelerator With Hardware-Algorithm Co-Design Techniques.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

IPOCIM: Artificial Intelligent Architecture Design Space Exploration With Scalable Ping-Pong Computing-in-Memory Macro.
IEEE Trans. Very Large Scale Integr. Syst., February, 2024

IRConStyle: Image Restoration Framework Using Contrastive Learning and Style Transfer.
CoRR, 2024

LIR: A Lightweight Baseline for Image Restoration.
CoRR, 2024

USR-LUT: A High-Efficient Universal Super Resolution Accelerator with Lookup Table.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

SuperHCA: A Super-Resolution Accelerator with Sparsity-Aware Heterogeneous Core Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

A RRAM-based High Energy-efficient Accelerator Supporting Multimodal Tasks for Virtual Reality Wearable Devices.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
ADAS: A High Computational Utilization Dynamic Reconfigurable Hardware Accelerator for Super Resolution.
ACM Trans. Reconfigurable Technol. Syst., September, 2023

HDSuper: Algorithm-Hardware Co-design for Light-weight High-quality Super-Resolution Accelerator.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
SCA: Search-Based Computing Hardware Architecture with Precision Scalable and Computation Reconfigurable Scheme.
Sensors, 2022

ReverSearch: Search-based energy-efficient Processing-in-Memory Architecture.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

TDPRO: Ultra-low Power ECG Processor with High-Precision Time-Domain Computing Engine.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

IPOCIM: Artificial Intelligent Processor with Adaptive Ping-pong Computing-in-Memory Architecture.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2021
Trend of Emerging Non-Volatile Memory for AI Processor.
Proceedings of the 18th International SoC Design Conference, 2021

Towards Intelligent-Edge Computing: Application, Architecture, Circuit, and Device Perspective.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

2016
C-brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization.
Proceedings of the 53rd Annual Design Automation Conference, 2016


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