Xingyu Pu

According to our database1, Xingyu Pu authored at least 4 papers between 2023 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2024
A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.
IEEE J. Solid State Circuits, September, 2024

A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits.
Sci. China Inf. Sci., October, 2023

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023


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