Bo Wang

Orcid: 0000-0002-6250-172X

Affiliations:
  • Tsinghua University, Institute of Microelectronics, Beijing, China


According to our database1, Bo Wang authored at least 21 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.
IEEE J. Solid State Circuits, September, 2024

Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2024

34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023
From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits.
Sci. China Inf. Sci., October, 2023

Evaluation Model for Current-Domain SRAM-based Computing-in-Memory Circuits.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

ShareFloat CIM: A Compute-In-Memory Architecture with Floating-Point Multiply-and-Accumulate Operations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Booth-based Digital Compute-in-Memory Marco for Processing Transformer Model.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021
Design Challenges and Methodology of High-Performance SRAM-Based Compute-in-Memory for AI Edge Devices.
Proceedings of the International Conference on UK-China Emerging Technologies, 2021

Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices.
Proceedings of the 18th International SoC Design Conference, 2021

2020
A 60 Gb/s-Level Coarse-Grained Reconfigurable Cryptographic Processor With Less Than 1-W Power.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

2019
Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018
Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017
Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks.
IEEE Trans. Inf. Forensics Secur., 2017

2016
Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture.
IEEE Trans. Inf. Forensics Secur., 2016

Dynamically reconfigurable architecture for symmetric ciphers.
Sci. China Inf. Sci., 2016

2015
A flexible and energy-efficient reconfigurable architecture for symmetric cipher processing.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

REPROC: A Dynamically Reconfigurable Architecture for Symmetric Cryptography (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015


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