Fahad Bin Muslim

Orcid: 0000-0002-4153-360X

According to our database1, Fahad Bin Muslim authored at least 12 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Power-Intent Systolic Array Using Modified Parallel Multiplier for Machine Learning Acceleration.
Sensors, 2023

2020
FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Implementation of Symbol Timing Recovery for Estimation of Clock Skew.
CoRR, 2020

Simulations and experimental validation of one cycle controlled nine-level inverter using FPGA.
Comput. Electr. Eng., 2020

2017
Energy-efficient hardware design based on high-level synthesis.
PhD thesis, 2017

LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow.
Microprocess. Microsystems, 2017

High-Level Synthesis for Semi-Global Matching: Is the Juice Worth the Squeeze?
IEEE Access, 2017

Efficient FPGA Implementation of OpenCL High-Performance Computing Applications via High-Level Synthesis.
IEEE Access, 2017

2016
Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL.
Proceedings of the Position Papers of the 2016 Federated Conference on Computer Science and Information Systems, 2016

High Performance and Low Power Monte Carlo Methods to Option Pricing Models via High Level Design and Synthesis.
Proceedings of the 2016 European Modelling Symposium, 2016

2015
Analysis and Implementation of the Semi-Global Matching 3D Vision Algorithm Using Code Transformations and High-Level Synthesis.
Proceedings of the IEEE 81st Vehicular Technology Conference, 2015

Low power methodology for an ASIC design flow based on high-level synthesis.
Proceedings of the 23rd International Conference on Software, 2015


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