Ciara Rafferty

Orcid: 0000-0002-3670-366X

Affiliations:
  • Queen's University Belfast, UK


According to our database1, Ciara Rafferty authored at least 29 papers between 2013 and 2025.

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Bibliography

2025
Evaluating Area-Time-Power Trade-offs in NTT Accelerators for Post-Quantum Cryptography.
Proceedings of the 38th IEEE International System-on-Chip Conference, 2025

An Enhanced Two-Step CPA Side-Channel Analysis Attack on ML-KEM.
Proceedings of the 22nd International Conference on Security and Cryptography, 2025

RejSCore: Rejection Sampling Core for Multivariate-based Public key Cryptography.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2025

2024
Evaluating NTT/INTT Implementation Styles for Post-Quantum Cryptography.
IEEE Embed. Syst. Lett., December, 2024

Deep Learning Enhanced Side Channel Analysis on CRYSTALS-Kyber.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

Efficient Soft Core Multiplier for Post Quantum Digital Signatures.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

Approximate Homomorphic Pre-Processing for CNNs.
Proceedings of the 20th International Conference on Security and Cryptography, 2023

2022
Acceleration of Post Quantum Digital Signature Scheme CRYSTALS-Dilithium on Reconfigurable Hardware.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2020
High Performance Modular Multiplication for SIDH.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Accelerating Homomorphic Encryption using Approximate Computing Techniques.
Proceedings of the 17th International Joint Conference on e-Business and Telecommunications, 2020

A Secure Algorithm for Rounded Gaussian Sampling.
Proceedings of the Cryptology and Network Security - 19th International Conference, 2020

2019
Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2019

2018
On Practical Discrete Gaussian Samplers for Lattice-Based Cryptography.
IEEE Trans. Computers, 2018

Addressing Side-Channel Vulnerabilities in the Discrete Ziggurat Sampler.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2018

Compact, Scalable, and Efficient Discrete Gaussian Samplers for Lattice-Based Cryptography.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Error Samplers for Lattice-Based Cryptography -Challenges, Vulnerabilities and Solutions.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Evaluation of Large Integer Multiplication Methods on Hardware.
IEEE Trans. Computers, 2017

Compact and provably secure lattice-based signatures in hardware.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Optimised Multiplication Architectures for Accelerating Fully Homomorphic Encryption.
IEEE Trans. Computers, 2016

Time-independent discrete Gaussian sampling for post-quantum cryptography.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Standard lattices in hardware.
Proceedings of the 53rd Annual Design Automation Conference, 2016


2015
Accelerating fully homomorphic encryption over the integers.
PhD thesis, 2015

2014
Accelerating integer-based fully homomorphic encryption using Comba multiplication.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Practical homomorphic encryption: A survey.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

High-Speed Fully Homomorphic Encryption Over the Integers.
Proceedings of the Financial Cryptography and Data Security, 2014

2013
Accelerating Fully Homomorphic Encryption over the Integers with Super-size Hardware Multiplier and Modular Reduction.
IACR Cryptol. ePrint Arch., 2013

Targeting FPGA DSP Slices for a Large Integer Multiplier for Integer Based FHE.
Proceedings of the Financial Cryptography and Data Security, 2013


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