Yeonam Yoon

Orcid: 0000-0003-2802-0444

According to our database1, Yeonam Yoon authored at least 11 papers between 2013 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs.
IEICE Trans. Electron., 2019

2018
A 6-bit 0.81-mW 700-MS/s SAR ADC With Sparkle-Code Correction, Resolution Enhancement, and Background Window Width Calibration.
IEEE J. Solid State Circuits, 2018

2017
A 0.7-V 0.6-µW 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction.
IEEE J. Solid State Circuits, 2017

A 6-bit 0.81mW 700-MS/s SAR ADC with sparkle-code correction, resolution enhancement, and background window width calibration.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A pipelined SAR ADC reusing the comparator as residue amplifier.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2015
A Scaling-Friendly Low-Power Small-Area ΔΣ ADC With VCO-Based Integrator and Intrinsic Mismatch Shaping Capability.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

A 0.04-mm<sup>2</sup> 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
A purely-VCO-based single-loop high-order continuous-time ΣΔ ADC.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A 10MHz-BW, 5.6mW, 70dB SNDR ΔΣ ADC using VCO-based integrators with intrinsic DEM.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A 1.8mW 2MHz-BW 66.5dB-SNDR ΔΣ ADC using VCO-based integrators with intrinsic CLA.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013


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