Yi-Ping Kuo

According to our database, Yi-Ping Kuo authored at least 4 papers between 2013 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction.

Yi-Ping Kuo, Po-Tsang Huang, Chung-Shiang Wu, Yu-Jie Liang, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang

Proceedings of the VLSI Design, Automation and Test, 2015

An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications.

Chung-Shiang Wu, Kai-Chun Lin, Yi-Ping Kuo, Po-Hung Chen, Yuan-Hua Chu, Wei Hwang

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems.

Pei-Chen Wu, Yi-Ping Kuo, Chung-Shiang Wu, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

2013

A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range.

Mei-Wei Chen, Ming-Hung Chang, Pei-Chen Wu, Yi-Ping Kuo, Chun-Lin Yang, Yuan-Hua Chu, Wei Hwang

Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013