Yifei Luo

Orcid: 0000-0003-0848-8605

According to our database1, Yifei Luo authored at least 13 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Online Open-Circuit Fault Diagnosis for Neutral Point Clamped Inverter Based on an Improved Convolutional Neural Network and Sample Amplification Method Under Varying Operating Conditions.
IEEE Trans. Instrum. Meas., 2024

A Passive Voltage-Balancing Method for Series-Connected SiC MOSFETs in Pulse Generator Based on Snubber Circuit.
IEEE Trans. Ind. Electron., 2024

2023
Characterization on the thermal field inside IGBT cells during switching based on TCAD modeling and Thermoreflectance imaging.
Microelectron. J., December, 2023

2022
An Improved Equivalent Circuit Model of SiC MOSFET and Its Switching Behavior Predicting Method.
IEEE Trans. Ind. Electron., 2022

Modeling of High-Voltage Nonpunch-Through PIN Diode Snappy Reverse Recovery and Its Optimal Suppression Method Based on RC Snubber Circuit.
IEEE Trans. Ind. Electron., 2022

CogTaskonomy: Cognitively Inspired Task Taxonomy Is Beneficial to Transfer Learning in NLP.
Proceedings of the 60th Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers), 2022

2021
Fatigue Mechanism of Die-Attach Joints in IGBTs Under Low-Amplitude Temperature Swings Based on 3D Electro-Thermal-Mechanical FE Simulations.
IEEE Trans. Ind. Electron., 2021

2020
Semantic Information Supplementary Pyramid Network for Dynamic Scene Deblurring.
IEEE Access, 2020

2019
An Improved Algorithm for Solving Scheduling Problems by Combining Generative Adversarial Network with Evolutionary Algorithms.
Proceedings of the 3rd International Conference on Computer Science and Application Engineering, 2019

2018
Temperature monitoring inside IGBT modules at forward bias from the cross section and its finite element analysis.
Microelectron. Reliab., 2018

2010
A 10B 200MHz pipeline ADC with minimal feedback penalty and 0.35pJ/conversion-step.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2009
A picosecond TDC architecture for multiphase PLLs.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2006
Triple-rail MOS current mode logic for high-speed self-timed pipeline applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006


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