Ying Zhang
Orcid: 0000-0001-7887-6510Affiliations:
- Tongji University, Shanghai, China
- Linköping University, Embedded Systems Lab, Sweden (former)
- Chinese Academy of Sciences, Institute of Computing Technology, Beijing, China (PhD 2011)
According to our database1,
Ying Zhang
authored at least 20 papers
between 2008 and 2024.
Collaborative distances:
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Bibliography
2024
Identifying Reliability High-Correlated Gates of Logic Circuits With Pearson Correlation Coefficient.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
2023
Parallel Software-Based Self-Testing with Bounded Model Checking for Kilo-Core Networks-on-Chip.
J. Comput. Sci. Technol., April, 2023
2022
BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature.
IEEE Trans. Very Large Scale Integr. Syst., 2022
2021
A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Very-Large-Scale Network-on-Chip.
ACM Trans. Design Autom. Electr. Syst., 2021
2020
Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Parallel Genetic Algorithm to Extend the Lifespan of Internet of Things in 5G Networks.
IEEE Access, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Wafer-Level NoC.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
J. Electron. Test., 2018
Proceedings of the IEEE International Test Conference in Asia, 2018
2017
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
Proceedings of the IEEE International Test Conference, 2017
2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2013
Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2013
2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects.
IEEE Trans. Very Large Scale Integr. Syst., 2011
2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
2009
J. Comput. Sci. Technol., 2009
2008
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Proceedings of the 17th IEEE Asian Test Symposium, 2008