Ying Zhang

According to our database, Ying Zhang authored at least 24 papers between 2008 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2025

Multiobjective Optimization in Logic Synthesis Based on TB-RM Dual Logic.

Yuhao Zhou, Zhen Wang, Xiangxue Kong, Hongyang Pan, Zhenxue He, Ying Zhang, Jianhui Jiang, Limin Xiao, Xiang Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2025

An Efficient Area and Reliability Optimization Method for MPRM Circuits Based on High-dimensional Genetic Algorithm.

Yuhao Zhou, Jianhui Jiang, Zhenxue He, Ying Zhang, Chengcheng Chen, Zhanhui Shi, Wei Zhang, Keying Yang

ACM Trans. Design Autom. Electr. Syst., March, 2025

2024

On Modeling and Detecting Trojans in Instruction Sets.

Ying Zhang, Aodi He, Jiaying Li, Ahmed Rezine, Zebo Peng, Erik Larsson, Tao Yang, Jianhui Jiang, Huawei Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

ARA-RCIV: Identifying Reliability-Critical Input Vectors of Logic Circuits Based on the Association Rules Analysis Approach.

Zhanhui Shi, Jie Xiao, Jianhui Jiang, Ying Zhang, Yuhao Zhou

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2024

Identifying Reliability High-Correlated Gates of Logic Circuits With Pearson Correlation Coefficient.

Zhanhui Shi, Jie Xiao, Jianhui Jiang, Ying Zhang, Yuhao Zhou

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

2023

Parallel Software-Based Self-Testing with Bounded Model Checking for Kilo-Core Networks-on-Chip.

Ying Zhang, Pengfei Ji, Pan-Wei Zhu, Zebo Peng, Huawei Li, Jian-Hui Jiang

J. Comput. Sci. Technol., April, 2023

2022

BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature.

Ying Zhang, Yi Ding, Zebo Peng, Huawei Li, Masahiro Fujita, Jianhui Jiang

IEEE Trans. Very Large Scale Integr. Syst., 2022

2021

A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Very-Large-Scale Network-on-Chip.

Ying Zhang, Xinpeng Hong, Zhongsheng Chen, Zebo Peng, Jianhui Jiang

ACM Trans. Design Autom. Electr. Syst., 2021

2020

Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors.

Ying Zhang, Krishnendu Chakrabarty, Zebo Peng, Ahmed Rezine, Huawei Li, Petru Eles, Jianhui Jiang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Parallel Genetic Algorithm to Extend the Lifespan of Internet of Things in 5G Networks.

Ying Zhang, Weihong Yu, Xiaodong Chen, Jianhui Jiang

IEEE Access, 2020

HIT: A Hidden Instruction Trojan Model for Processors.

Jiaqi Zhang, Ying Zhang, Huawei Li, Jianhui Jiang

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Wafer-Level NoC.

Zhongsheng Chen, Ying Zhang, Zebo Peng, Jianhui Jiang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Thermal-aware SoC Test Scheduling with Voltage/Frequency Scaling and Test Partition.

Ying Zhang, Li Ling, Jianhui Jiang, Jie Xiao

J. Electron. Test., 2018

Small Trojan Testing Using Bounded Model Checking.

Ying Zhang, Lu Yu, Huawei Li, Jianhui Jiang

Proceedings of the IEEE International Test Conference in Asia, 2018

2017

High-level Fault Diagnosis on network-on-chip using path tracking.

Minhui Ke, Ying Zhang, Jianhui Jiang

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

Software-based online self-testing of network-on-chip using bounded model checking.

Ying Zhang, Krishnendu Chakrabarty, Huawei Li, Jianhui Jiang

Proceedings of the IEEE International Test Conference, 2017

2015

Temperature-aware software-based self-testing for delay faults.

Ying Zhang, Zebo Peng, Jianhui Jiang, Huawei Li, Masahiro Fujita

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2013

Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors.

Ying Zhang, Huawei Li, Xiaowei Li

IEEE Trans. Very Large Scale Integr. Syst., 2013

2012

Automatic Test Program Generation for Out-of-Order Superscalar Processors.

Ying Zhang, Ahmed Rezine, Petru Eles, Zebo Peng

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects.

Ying Zhang, Huawei Li, Yinghua Min, Xiaowei Li

IEEE Trans. Very Large Scale Integr. Syst., 2011

2010

Software-Based Self-Testing of Processors Using Expanded Instructions.

Ying Zhang, Huawei Li, Xiaowei Li

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Selected Crosstalk Avoidance Code for Reliable Network-on-Chip.

Ying Zhang, Huawei Li, Xiaowei Li

J. Comput. Sci. Technol., 2009

2008

Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects.

Ying Zhang, Huawei Li, Xiaowei Li, Yu Hu

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance.

Ying Zhang, Huawei Li, Xiaowei Li

Proceedings of the 17th IEEE Asian Test Symposium, 2008