Yoshihito Nishizaki

According to our database, Yoshihito Nishizaki authored at least 3 papers between 1990 and 2005.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2005

Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression.

Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2003

Testing DSM ASIC With Static, \DeltaIDDQ, And Dynamic Test Suite: Implementation And Results.

Yoshihito Nishizaki, Osamu Nakayama, Chiaki Matsumoto, Yoshitaka Kimura, Toshimi Kobayashi, Hiroyuki Nakamura

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

1990

Logic Synthesis for Programmable Gate Arrays.

Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990