Hwasuk Cho
According to our database1,
Hwasuk Cho
authored at least 10 papers
between 2017 and 2021.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2021
A 26GHz Fractional-N Digital Frequency Synthesizer Leveraging Noise Profiles of Three Functional Stages.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage.
IEEE J. Solid State Circuits, 2021
2020
A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
A Multilayer-Learning Current-Mode Neuromorphic System With Analog-Error Compensation.
IEEE Trans. Biomed. Circuits Syst., 2019
2018
An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table.
IEEE Trans. Biomed. Circuits Syst., 2018
A 0.3-to-1.2V frequency-scalable fractional-N ADPLL with a speculative dual-referenced interpolating TDC.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
A 250-µW 2.4-GHz Fast-Lock Fractional-N Frequency Generation for Ultralow-Power Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A Low-Power Wide Dynamic-Range Current Readout Circuit for Ion-Sensitive FET Sensors.
IEEE Trans. Biomed. Circuits Syst., 2017
8.7 A 0.0047mm<sup>2</sup> highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHz.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017