Yousef Iskander

According to our database1, Yousef Iskander authored at least 10 papers between 2010 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment Using Information Flow Tracking and Pattern Generation.
ACM Trans. Design Autom. Electr. Syst., 2020

The Big Hack Explained: Detection and Prevention of PCB Supply Chain Implants.
ACM J. Emerg. Technol. Comput. Syst., 2020

2019
Security and Trust Verification of IoT SoCs.
Proceedings of the Security and Fault Tolerance in Internet of Things, 2019

2018
Guest Editorial: Hardware Reverse Engineering and Obfuscation.
J. Hardw. Syst. Secur., 2018

Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution.
Proceedings of the IEEE International Test Conference, 2018

2014
High-Level Abstractions and Modular Debugging for FPGA Design Validation.
ACM Trans. Reconfigurable Technol. Syst., 2014

2011
Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010
PATIS: Using partial configuration to improve static FPGA design productivity.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Using partial reconfiguration and high-level models to accelerate FPGA design validation.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Accelerating FPGA development through the automatic parallel application of standard implementation tools.
Proceedings of the International Conference on Field-Programmable Technology, 2010


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