Frank Vahid

Stefano Lonardi

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A one-shot configurable-cache tuner for improved energy and performance.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A Self-Tuning Configurable Cache.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

Thread warping: a framework for dynamic synthesis of thread accelerators.

[BibT_eX]

[DOI]

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006

Warp Processors.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2006

A code refinement methodology for performance-improved synthesis from C.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Conjoining soft-core FPGA processors.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Application-specific customization of parameterized FPGA soft-core processors.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Automated Application-Specific Tuning of Parameterized Sensor-Based Embedded System Building Blocks.

[BibT_eX]

[DOI]

Susan Lysecky

Proceedings of the UbiComp 2006: Ubiquitous Computing, 2006

Automated Generation of Basic Custom Sensor-Based Embedded Computing Systems Guided by End-User Optimization Criteria.

[BibT_eX]

[DOI]

Susan Lysecky

Proceedings of the UbiComp 2006: Ubiquitous Computing, 2006

Configurable cache subsetting for fast cache tuning.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

A highly configurable cache for low energy embedded systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2005

Frequent Loop Detection Using Efficient Nonintrusive On-Chip Hardware.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

eBlocks - an enabling technology for basic sensor based systems.

[BibT_eX]

[DOI]

Proceedings of the Fourth International Symposium on Information Processing in Sensor Networks, 2005

New decompilation techniques for binary-level co-processor generation.

[BibT_eX]

[DOI]

Greg Stiff

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

A first look at the interplay of code reordering and configurable caches.

[BibT_eX]

[DOI]

Nikil D. Dutt

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Techniques for synthesizing binaries to an advanced register/memory structure.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only).

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation.

[BibT_eX]

[DOI]

Sheldon X.-D. Tan

Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

System Synthesis for Networks of Programmable Blocks.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Hardware/software partitioning of software binaries: a case study of H.264 decode.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

A logic block enabling logic configuration by non-experts in sensor networks.

[BibT_eX]

[DOI]

Proceedings of the Extended Abstracts Proceedings of the 2005 Conference on Human Factors in Computing Systems, 2005

2004

A fast on-chip profiler memory using a pipelined binary tree.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

A self-tuning cache architecture for embedded systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2004

Energy savings and speedups from partitioning critical software loops to hardware in embedded systems.

[BibT_eX]

[DOI]

Shawn Nematbakhsh

ACM Trans. Embed. Comput. Syst., 2004

Applications and experiments with eBlocks - electronic blocks for basic sensor-based systems.

[BibT_eX]

[DOI]

Kelly Downey

Proceedings of the First Annual IEEE Communications Society Conference on Sensor and Ad Hoc Communications and Networks, 2004

A quantitative analysis of the speedup factors of FPGAs over processors.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Low Static-Power Frequent-Value Data Caches.

[BibT_eX]

[DOI]

Jun Yang

Proceedings of the 2004 Design, 2004

Using a Victim Buffer in an Application-Specific Memory Hierarchy.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Automatic Tuning of Two-Level Caches to Embedded Applications.

[BibT_eX]

[DOI]

Nikil D. Dutt

Proceedings of the 2004 Design, 2004

Dynamic FPGA routing for just-in-time FPGA compilation.

[BibT_eX]

[DOI]

Sheldon X.-D. Tan

Proceedings of the 41th Design Automation Conference, 2004

Tuning Caches to Applications for Low-Energy Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003

Tiny instruction caches for low power embedded systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2003

Highly configurable platforms for embedded computing systems.

[BibT_eX]

[DOI]

Microelectron. J., 2003

Making the Best of Those Extra Transistors.

[BibT_eX]

IEEE Des. Test Comput., 2003

The Softening of Hardware.

[BibT_eX]

[DOI]

Computer, 2003

A Way-Halting Cache for Low-Energy High-Performance Systems.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2003

Cache Configuration Exploration on Prototyping Platforms.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

Embedded System Design: UCR's Undergraduate Three-Course Sequence.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Profiling tools for hardware/software partitioning of embedded applications.

[BibT_eX]

[DOI]

Proceedings of the 2003 Conference on Languages, 2003

Energy Benefits of a Configurable Line Size Cache for Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

A Highly-Configurable Cache Architecture for Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

Dynamic hardware/software partitioning: a first approach.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

On-chip logic minimization.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

A codesigned on-chip logic minimizer.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

First results with eBlocks: embedded systems building blocks.

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Frequent loop detection using efficient non-intrusive on-chip hardware.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Compilers, 2003

2002

Instruction-based system-level power evaluation of system-on-a-chip peripheral cores.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Partitioning sequential programs for CAD using a three-step approach.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2002

Prefetching for improved bus wrapper performance in cores.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2002

Platune: a tuning framework for system-on-a-chip platforms.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Power Estimator Development for Embedded System Memory Tuning.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2002

Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2002

Improving Software Performance with Configurable Logic.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2002

Tuning of Cache Ways and Voltage for Low-Energy Embedded System Platforms.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2002

Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2002

Tuning of Loop Cache Architectures to Programs in Embedded System Design.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

A power-configurable bus for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Dynamic Loop Caching Meets Preloaded Loop Caching - A Hybrid Approach.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Hardware/software partitioning of software binaries.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Synthesis of customized loop caches for core-based embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Using On-Chip Configurable Logic to Reduce Embedded System Software Energy.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

A fast on-chip profiler memory.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

Codesign-extended applications.

[BibT_eX]

[DOI]

Brian Grattan

Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

Embedded system design - a unified hardware / software introduction.

[BibT_eX]

Wiley-VCH, ISBN: 978-0-471-45303-1, 2002

2001

Evaluating power consumption of parameterized cache and bus architectures in system-on-a-chip designs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Propagating constants past software to hardware peripherals in fixed-application embedded systems.

[BibT_eX]

[DOI]

Rilesh Patel

SIGARCH Comput. Archit. News, 2001

Platform Tuning for Embedded Systems Design.

[BibT_eX]

[DOI]

Computer, 2001

A self-optimizing embedded microprocessor using a loop table for low power.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Trace-driven system-level power evaluation of system-on-a-chip peripheral cores.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

2000

Experiments with the Peripheral Virtual Component Interface.

[BibT_eX]

[DOI]

Proceedings of the 13th International Symposium on System Synthesis, 2000

Techniques for Reducing Read Latency of Core Bus Wrappers.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

Parameterized system design.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

A first-step towards an architecture tuning methodology for low power.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Conference on Compilers, 2000

A hybrid approach for core-based system-level power modeling.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2000, 2000

1999

Procedure cloning: a transformation for improved system-level functional partitioning.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1999

Techniques for minimizing and balancing I/O during functional partitioning.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Pre-Fetching for Improved Core Interfacing.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on System Synthesis, 1999

Interface and cache power exploration for core-based embedded system design.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

FSMD Functional Partitioning for Low Power.

[BibT_eX]

[DOI]

Enoch Hwang

Yu-Chin Hsu

Proceedings of the 1999 Design, 1999

The case for a configure-and-execute paradigm.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998

SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1998

Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance.

[BibT_eX]

[DOI]

Yu-Chin Hsu

ACM Trans. Design Autom. Electr. Syst., 1998

Incorporating Cores into System-Level Specification.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on System Synthesis, 1998

A Three-Step Approach to the Functional Partitioning of Large Behavioral Processes.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on System Synthesis, 1998

Interface Exploration for Reduced Power in Core-Based Systems.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on System Synthesis, 1998

System-level exploration with SpecSyn.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

1997

Extending the Kernighan/Lin Heuristic for Hardware and Software Functional Partitioning.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 1997

Port Calling: A Transformation for Reducing I/O during Multi-Package Functional Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on System Synthesis, 1997

I/O and Performance Tradeoffs with the FunctionBus During Multi-FPGA Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997

An Object-Oriented Communication Library for Hardware-Software CoDesign.

[BibT_eX]

[DOI]

Linus Tauro

Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

Modifying Min-Cut for Hardware and Software Functional Partitioning.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

1996

System design methodologies: aiming at the 100 h design cycle.

[BibT_eX]

[DOI]

Loganath Ramachandran

Peter Fung

IEEE Trans. Very Large Scale Integr. Syst., 1996

A Comparison of Functional and Structural Partitioning.

[BibT_eX]

[DOI]

Yu-Chin Hsu

Proceedings of the 9th International Symposium on System Synthesis, 1996

Towards a Model for Hardware and Software Functional Partitioning.

[BibT_eX]

[DOI]

Proceedings of the Forth International Workshop on Hardware/Software Codesign, 1996

1995

Incremental hardware estimation during hardware/software functional partitioning.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1995

SpecCharts: a VHDL front-end for embedded systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Specification and Design of Embedded Hardware-Software Systems.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1995

Clustering for improved system-level functional partitioning.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Procedure exlining: a transformation for improved system and behavioral synthesis.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

Closeness metrics for system-level functional partitioning.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'95, 1995

Procedure exlining: a new system-level specification transformation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'95, 1995

SLIF: a specification-level intermediate format for system design.

[BibT_eX]

[DOI]

Proceedings of the 1995 European Design and Test Conference, 1995

1994

A transformation for integrating VHDL behavioral specification with synthesis and software generation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'94, 1994

A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning.

[BibT_eX]

[DOI]

Jie Gong

Proceedings of the Proceedings EURO-DAC'94, 1994

100-hour design cycle: a test case.

[BibT_eX]

[DOI]

Loganath Ramachandran

Proceedings of the Proceedings EURO-DAC'94, 1994

A System-Design Methodology: Executable-Specification Refinement.

[BibT_eX]

[DOI]

Daniel Gajski

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

Synthesis of functions and procedures in behavioral VHDL.

[BibT_eX]

[DOI]

Loganath Ramachandran