Harry Hsieh

Affiliations:
  • University of California, Riverside, USA


According to our database1, Harry Hsieh authored at least 39 papers between 1994 and 2009.

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Bibliography

2009
Runtime deadlock analysis for system level design.
Des. Autom. Embed. Syst., 2009

Memory subsystem simulation in software TLM/T models.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Fast and accurate performance simulation of embedded software for MPSoC.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Partial order method for timed simulation of system-level MPSoC designs.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Software optimization for MPSoC: a mpeg-2 decoder case study.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

2007
Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Framework for fast and accurate performance simulation of multiprocessor systems.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

Bridging RTL and gate: correlating different levels of abstraction for design debugging.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007

2006
Verification Approach of Metropolis Design Framework for Embedded Systems.
Int. J. Parallel Program., 2006

Runtime Deadlock Analysis of SystemC Designs.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Communication and co-simulation infrastructure for heterogeneous system integration.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
eBlocks - an enabling technology for basic sensor based systems.
Proceedings of the Fourth International Symposium on Information Processing in Sensor Networks, 2005

Assertion-Based Design Exploration of DVS in Network Processor Architectures.
Proceedings of the 2005 Design, 2005

System Synthesis for Networks of Programmable Blocks.
Proceedings of the 2005 Design, 2005

Simulation based deadlock analysis for system level designs.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Logic of constraints: a quantitative performance and functional constraint formalism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Assertion Based Verification and Analysis of Network Processor Architectures.
Des. Autom. Embed. Syst., 2004

Assertion-based power/performance analysis of network processor architectures.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Utilizing Formal Assertions for System Design of Network Processors.
Proceedings of the 2004 Design, 2004

2003
Formal Verification for Embedded System Designs.
Des. Autom. Embed. Syst., 2003

Metropolis: An Integrated Electronic System Design Environment.
Computer, 2003

Verifying LOC based functional and performance constraints.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Automatic Generation of Simulation Monitors from Quantitative Constraint Formula.
Proceedings of the 2003 Design, 2003

Automatic trace analysis for logic of constraints.
Proceedings of the 40th Design Automation Conference, 2003

First results with eBlocks: embedded systems building blocks.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Case Studies of Model Checking for Embedded System Designs.
Proceedings of the 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 2003

Simulation Trace Verification for Quantitative Constraints.
Proceedings of the Embedded Software for SoC, 2003

2002
Formal verification of embedded system designs at multiple levels of abstraction.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

2001
Synchronous approach to the functional equivalence of embeddedsystem implementations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

2000
Refining abstract equivalence analysis for embedded system design.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

Efficient methods for embedded system design space exploration.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Synthesis of software programs for embedded control applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Synchronous equivalence for embedded systems: a tool for design exploration.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1997
Modeling micro-controller peripherals for high-level co-simulation and synthesis.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

1996
A case study in computer-aided co-design of embedded controllers.
Des. Autom. Embed. Syst., 1996

Formal Verification of Embedded Systems based on CFSM Networks.
Proceedings of the 33st Conference on Design Automation, 1996

1995
Synthesis of Software Programs for Embedded Control Applications.
Proceedings of the 32st Conference on Design Automation, 1995

1994
Hardware-software codesign of embedded systems.
IEEE Micro, 1994

A case study in computer-aided codesign of embedded controllers.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994


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