Yu-Hsian Chen

According to our database, Yu-Hsian Chen authored at least 3 papers between 2013 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression.

Ming-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2014

A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists.

Chao-Kuei Chung, Chien-Yu Lu, Zhi-Hao Chang, Shyh-Jye Jou, Ching-Te Chuang, Ming-Hsien Tu, Yu-Hsian Chen, Yong-Jyun Hu, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

2013

A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression.

Ming-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013