Yu Liu

Orcid: 0000-0001-9789-0959

Affiliations:
  • Anhui University, School of Integrated Circuits, Hefei, China
  • University of Science and Technology of China (USTC), Hefei, China (PhD 2021)


According to our database1, Yu Liu authored at least 21 papers between 2018 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
Analysis and Design of Memory Testing Algorithm for Computing-in-Memory Using MBIST.
ACM J. Emerg. Technol. Comput. Syst., April, 2026

A 28 nm 1.3 TFLOPS/mm<sup>2</sup> Floating-Point SRAM-Based CIM Macro With Asynchronous Normalization and Parallel Sorting Alignment for AI-Edge Chip.
IEEE Trans. Very Large Scale Integr. Syst., March, 2026

BridgeDiff: Bridging Human Observations and Flat-Garment Synthesis for Virtual Try-Off.
CoRR, March, 2026

A Floating-Point CIM Macro Featuring Asymmetric Exponent Encoding and Adaptive Mantissa Truncation for High-Efficiency AI Edge Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

A Multiplication-Free Floating-Point CIM Architecture with a 5-Bit Approximate Squaring Circuit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025
A 28-nm 9T1C SRAM-Based CIM Macro With Hierarchical Capacitance Weighting and Two-Step Capacitive Comparison ADCs for CNNs.
IEEE Trans. Very Large Scale Integr. Syst., July, 2025

High-Efficiency Calibration Methodology of Interchannel Mismatches in TIADCs Based on Digital Orthogonal Local Oscillation Signal.
IEEE Trans. Instrum. Meas., 2025

TSCIM: A 28nm Transposed Stochastic CIM Macro for On-Chip Training and Inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A Floating-Point SRAM-based CIM Macro with Asynchronous Normalization and Parallel Sorting Alignment.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A Signed-Transfer SRAM Computing-in-Memory Macro with In-Column Reconfiguration Dac and 2Bit/Cycle Quantization.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025

ChargeFloat-TQ: A Charge-Domain-Based Tracking-Quantized Floating-Point Computing-in-Memory Accelerator Macro.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025

A 28Nm Floating-Point SRAM-Based CIM Macro with Shifting-in-Memory Exponent Normalization and Mantissa Alignment.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025

A Derivative-Sign Discrimination Based Calibration Scheme for Timing Skew in Dual-Channel TIADCs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025

2024
Domain-aware double attention network for zero-shot sketch-based image retrieval with similarity loss.
Vis. Comput., May, 2024

Semi-ssPTM: A Web Server for Species-Specific Lysine Post-Translational Modification Site Prediction by Semi-Supervised Domain Adaptation.
IEEE Trans. Instrum. Meas., 2024

A 28-nm 9T SRAM-based CIM macro with capacitance weighting module and redundant array-assisted ADC.
Microelectron. J., 2024

2022
TSDLPP: A Novel Two-Stage Deep Learning Framework For Prognosis Prediction Based on Whole Slide Histopathological Images.
IEEE ACM Trans. Comput. Biol. Bioinform., 2022

2021
Semi-HIC: A novel semi-supervised deep learning method for histopathological image classification.
Comput. Biol. Medicine, 2021

2019
DeepPhos: prediction of protein phosphorylation sites with deep learning.
Bioinform., 2019

Adversarially Regularized U-Net-based GANs for Facial Attribute Modification and Generation.
IEEE Access, 2019

2018
Picowatt 0.5 V supply with 3 ppm/°C CMOS voltage reference for energy harvesting system.
IEICE Electron. Express, 2018


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