Yudong Zhang
Orcid: 0000-0002-7280-1486Affiliations:
- Apple Inc., San Diego, SerDes Design Engineer, CA, USA
- Columbia University, Department of electrical engineering, NY, USA (PhD 2021)
- Cisco Systems, Allentown, PA, USA
- Tsinghua University, Institute of Microelectronics, Beijing, China (former)
According to our database1,
Yudong Zhang
authored at least 6 papers
between 2015 and 2022.
Collaborative distances:
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Bibliography
2022
Analysis of Injection-Locked Ring Oscillators for Quadrature Clock Generation in Wireline or Optical Transceivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Multi-Phase Clock Generation for Phase Interpolation With a Multi-Phase, Injection-Locked Ring Oscillator and a Quadrature DLL.
IEEE J. Solid State Circuits, 2022
2021
11.4 A High-Accuracy Multi-Phase Injection-Locked 8-Phase 7GHz Clock Generator in 65nm with 7b Phase Interpolators for High-Speed Data Links.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2018
A Reconfigurable Architecture Using a Flexible LO Modulator to Unify High-Sensitivity Signal Reception and Compressed-Sampling Wideband Signal Detection.
IEEE J. Solid State Circuits, 2018
2017
A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2015
A 0.35-0.5-V 18-152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2015