Yue Zhao

Orcid: 0000-0002-3341-6294

According to our database1, Yue Zhao authored at least 8 papers between 2022 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
A 28-nm 9T1C SRAM-Based CIM Macro With Hierarchical Capacitance Weighting and Two-Step Capacitive Comparison ADCs for CNNs.
IEEE Trans. Very Large Scale Integr. Syst., July, 2025

2024
Configurable in-memory computing architecture based on dual-port SRAM.
Microelectron. J., 2024

Cross-coupled 4T2R multi-logic in-memory computing circuit design.
Microelectron. J., 2024

SRAM-Based Digital CIM Macro for Linear Interpolation and MAC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
In-Memory Transposable Multibit Multiplication Based on Diagonal Symmetry Weight Block.
IEEE Trans. Very Large Scale Integr. Syst., September, 2023

In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations.
IEEE J. Solid State Circuits, May, 2023

2022
Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2022

An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset.
Microelectron. J., 2022


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