Narumi Sakashita

According to our database, Narumi Sakashita authored at least 9 papers between 1988 and 1999.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1999

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme.

Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura

IEEE J. Solid State Circuits, 1999

1997

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique.

Ken'ichi Shimomura, Hiroki Shimano, Narumi Sakashita, Fumihiro Okuda, Toshiyuki Oashi, Yasuo Yamaguchi, Takahisa Eimori, Masahide Inuishi, Kazutami Arimoto, Shigeto Maegawa, Yasuo Inoue, Shinji Komori, Kazuo Kyuma

IEEE J. Solid State Circuits, 1997

Reduction of the Test Time for Mass Produced LSI Devices by Genetic Algorithms.

T. Iwamoto, S. Kobashi, Narumi Sakashita, J. Mitsuishi, Ken-ichi Tanaka, Kazuo Kyuma

Proceedings of the Progress in Connectionist-Based Information Systems: Proceedings of the 1997 International Conference on Neural Information Processing and Intelligent Information Systems, 1997

1996

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture.

Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Fumihiro Okuda, Hiroki Shimano, Satoshi Yamakawa, Masaki Tsukude, Kazutami Arimoto, Shinji Baba, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe

IEEE J. Solid State Circuits, 1996

A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM.

Narumi Sakashita, Fumihiro Okuda, Ken'ichi Shimomura, Hiroki Shimano, Mitsuhiro Hamada, Tetsuo Tada, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1993

Fuzzy inference and fuzzy inference processor.

Kazuo Nakamura, Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Takeshi Tokuda

IEEE Micro, 1993

A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC.

Eiichi Teraoka, Toru Kengaku, Ikuo Yasui, Kazuyuki Ishikawa, Takahiro Matsuo, Hideyuki Wakada, Narumi Sakashita, Yukihiko Shimazu, Takeshi Tokuda

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1990

Built-in self-test in a 24 bit floating point digital signal processor.

Narumi Sakashita, Hisako Sawai, Eiichi Teraoka, Toshiki Fugiyama, Toru Kengaku, Yukihiko Shimazu, Takeshi Tokuda

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1988

A macrocell approach for VLSI processor design.

Takeshi Tokuda, Jiro Korematsu, Yukihiko Shimazu, Narumi Sakashita, Tohru Kengaku, Toshiki Fugiyama, Takio Ohno, Osamu Tomisawa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988