Yun Chiu

According to our database, Yun Chiu authored at least 58 papers between 2004 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

An IF-Sampling CMOS S/H Calibration Technique With Analog HPF Slope Estimation.

Yanqing Li, Yun Chiu

IEEE Trans. Circuits Syst. II Express Briefs, 2022

2021

Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC).

Yun Chiu, Man-Kay Law, Nagendra Krishnapura, Jason T. Stauth, Jeffrey S. Walling

IEEE J. Solid State Circuits, 2021

2020

A Compact Calibration Model for Linearizing CMOS Sample-and-Hold Circuits.

Yanqing Li, Yuan Zhou, Yun Chiu

IEEE Trans. Circuits Syst., 2020

2019

A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC.

Yuan Zhou, Benwei Xu, Yun Chiu

IEEE J. Solid State Circuits, 2019

A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS.

Hongda Xu, Hai Huang, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu

IEEE J. Solid State Circuits, 2019

2018

A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS.

Shuang Zhu, Bo Wu, Yongda Cai, Yun Chiu

IEEE J. Solid State Circuits, 2018

A 9-bit 215 MS/s Folding-Flash Time-to-Digital Converter Based on Redundant Remainder Number System in 45-nm CMOS.

Bo Wu, Shuang Zhu, Yuan Zhou, Yun Chiu

IEEE J. Solid State Circuits, 2018

2017

A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS.

Benwei Xu, Yuan Zhou, Yun Chiu

IEEE J. Solid State Circuits, 2017

A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation.

Hai Huang, Hongda Xu, Brian Elies, Yun Chiu

IEEE J. Solid State Circuits, 2017

A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer.

Hai Huang, Ling Du, Yun Chiu

IEEE J. Solid State Circuits, 2017

An 8b 1.39GS/S 0.85V two-step ADC with background comparator offset calibration.

Sudipta Sarkar, Benwei Xu, Brian Elies, Yun Chiu

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS.

Hongda Xu, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1dB SNDR variation.

Hai Huang, Sudipta Sarkar, Brian Elies, Yun Chiu

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

A Skew-Free 10 GS/s 6 bit CMOS ADC With Compact Time-Domain Signal Folding and Inherent DEM.

Shuang Zhu, Benwei Xu, Bo Wu, Kiran Soppimath, Yun Chiu

IEEE J. Solid State Circuits, 2016

A 24.7 mW 65 nm CMOS SAR-Assisted CT ΔΣ Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR.

Bo Wu, Shuang Zhu, Benwei Xu, Yun Chiu

IEEE J. Solid State Circuits, 2016

A 23mW 24GS/s 6b Time-interleaved hybrid two-step ADC in 28nm CMOS.

Benwei Xu, Yuan Zhou, Yun Chiu

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

15.1 A 24.7mW 45MHz-BW 75.3dB-SNDR SAR-assisted CT ΔΣ modulator with 2nd-order noise coupling in 65nm CMOS.

Bo Wu, Shuang Zhu, Benwei Xu, Yun Chiu

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A smart ECG sensor with in-situ adaptive motion-artifact compensation for dry-contact wearable healthcare devices.

Shuang Zhu, Jingyi Song, Balaji Chellappa, Ali Enteshari, Tuo Shan, Mengxun He, Yun Chiu

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2015

Comprehensive Background Calibration of Time-Interleaved Analog-to-Digital Converters.

Benwei Xu, Yun Chiu

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

PN-Assisted Deterministic Digital Background Calibration of Multistage Split-Pipelined ADC.

Sudipta Sarkar, Yuan Zhou, Brian Elies, Yun Chiu

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector.

Yuan Zhou, Benwei Xu, Yun Chiu

IEEE J. Solid State Circuits, 2015

A 40 nm CMOS Derivative-Free IF Active-RC BPF With Programmable Bandwidth and Center Frequency Achieving Over 30 dBm IIP3.

Bo Wu, Yun Chiu

IEEE J. Solid State Circuits, 2015

A 0.073-mm² 10-GS/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEM.

Shuang Zhu, Benwei Xu, Bo Wu, Kiran Soppimath, Yun Chiu

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

IRD Digital Background Calibration of SAR ADC With Coarse Reference ADC Acceleration.

Guanhua Wang, Foti Kacani, Yun Chiu

IEEE Trans. Circuits Syst. II Express Briefs, 2014

A 15-MHz Bandwidth 1-0 MASH Σ Δ ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR.

Seung-Chul Lee, Yun Chiu

IEEE J. Solid State Circuits, 2014

A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration.

Yuan Zhou, Benwei Xu, Yun Chiu

Proceedings of the Symposium on VLSI Circuits, 2014

PN-assisted deterministic digital calibration of split two-step ADC to over 14-bit accuracy.

Sudipta Sarkar, Yuan Zhou, Yun Chiu

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A 9-bit 215-MS/s folding-flash time-to-digital converter based on redundant remainder number system.

Bo Wu, Shuang Zhu, Yuan Zhou, Yun Chiu

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

An 85-225MHz Chebyshev-II active-RC BPF with programmable BW and CF achieving over 30dBm IIP3 in 40nm CMOS.

Bo Wu, Yun Chiu

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

Digital calibration of inter-stage nonlinear errors in pipelined SAR ADC.

Yuan Zhou, Yun Chiu

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Background calibration of time-interleaved ADC using direct derivative information.

Benwei Xu, Yun Chiu

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Fast FPGA emulation of background-calibrated SAR ADC with internal redundancy dithering.

Guanhua Wang, Yun Chiu

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

A 15 MHz to 600 MHz, 20 mW, 0.38 mm² Split-Control, Fast Coarse Locking Digital DLL in 0.13 µ m CMOS.

Sebastian Hoyos, Cheongyuen W. Tsang, Johan P. Vanderhaegen, Yun Chiu, Yasutoshi Aibara, Haideh Khorramabadi, Borivoje Nikolic

IEEE Trans. Very Large Scale Integr. Syst., 2012

Time-Interleaved Analog-to-Digital Conversion With Online Adaptive Equalization.

Wenbo Liu, Yun Chiu

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

An 85dB SFDR 67dB SNDR 8OSR 240MS/s ΔΣ ADC with nonlinear memory error calibration.

Seung-Chul Lee, Brian Elies, Yun Chiu

Proceedings of the Symposium on VLSI Circuits, 2012

A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration.

Wenbo Liu, Pingli Huang, Yun Chiu

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

Digital Calibration of Capacitor Mismatch in Sigma-Delta Modulators.

Seung-Chul Lee, Yun Chiu

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration.

Wenbo Liu, Pingli Huang, Yun Chiu

IEEE J. Solid State Circuits, 2011

SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration.

Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu

IEEE J. Solid State Circuits, 2011

Equalization techniques for nonlinear analog circuits.

Yun Chiu

IEEE Commun. Mag., 2011

2010

A Virtual-ADC Digital Background Calibration Technique for Multistage A/D Conversion.

Bei Peng, Hao Li, Seung-Chul Lee, Pingfen Lin, Yun Chiu

IEEE Trans. Circuits Syst. II Express Briefs, 2010

An Offset Double Conversion Technique for Digital Calibration of Pipelined ADCs.

Bei Peng, Hao Li, Pingfen Lin, Yun Chiu

IEEE Trans. Circuits Syst. II Express Briefs, 2010

Digital Calibration of Nonlinear Memory Errors in Sigma-Delta Modulators.

Seung-Chul Lee, Yun Chiu

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A Four-Channel Beamforming Down-Converter in 90-nm CMOS Utilizing Phase-Oversampling.

Richard Tseng, Hao Li, Dae Hyun Kwon, Yun Chiu, Ada S. Y. Poon

IEEE J. Solid State Circuits, 2010

Digitally Equalized CMOS Transmitter Front-End With Integrated Power Amplifier.

Dae Hyun Kwon, Hao Li, Yuchun Chang, Richard Tseng, Yun Chiu

IEEE J. Solid State Circuits, 2010

A 12b 22.5/45MS/s 3.0mW 0.059mm² CMOS SAR ADC achieving over 90dB SFDR.

Wenbo Liu, Pingli Huang, Yun Chiu

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 5.8-mW, 20-MHz, 4th-order programmable elliptic filter achieving over -80-dB IM3.

Peiyuan Wan, Yun Chiu, Pingfen Lin

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration.

Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

A Fast Digital Predistortion Algorithm for Radio-Frequency Power Amplifier Linearization With Loop Delay Compensation.

Hao Li, Dae Hyun Kwon, Deming Chen, Yun Chiu

IEEE J. Sel. Top. Signal Process., 2009

A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization.

Wenbo Liu, Yuchun Chang, Szukang Hsien, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

CMOS RF transmitter with integrated power amplifier utilizing digital equalization.

Dae Hyun Kwon, Hao Li, Yuchun Chang, Richard Tseng, Yun Chiu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

A Mixed-Signal Vector Modulator for Eigenbeamforming Receivers.

Richard Tseng, Ada S. Y. Poon, Yun Chiu

IEEE Trans. Circuits Syst. II Express Briefs, 2008

A 15 MHz - 600 MHz, 20 mW, 0.38 mm2, fast coarse locking digital DLL in 0.13μm CMOS.

Sebastian Hoyos, Cheongyuen W. Tsang, Johan P. Vanderhaegen, Yun Chiu, Yasutoshi Aibara, Haideh Khorramabadi, Borivoje Nikolic

Proceedings of the ESSCIRC 2008, 2008

Background ADC calibration in digital domain.

Cheongyuen W. Tsang, Yun Chiu, Johan P. Vanderhaegen, Sebastian Hoyos, Charles Chen, Robert W. Brodersen, Borivoje Nikolic

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCs.

Pingli Huang, Yun Chiu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005

Scaling of analog-to-digital converters into ultra-deep-submicron CMOS.

Yun Chiu, Borivoje Nikolic, Paul R. Gray

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004

Least mean square adaptive digital background calibration of pipelined analog-to-digital converters.

Yun Chiu, Cheongyuen W. Tsang, Borivoje Nikolic, Paul R. Gray

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR.

Yun Chiu, Paul R. Gray, Borivoje Nikolic

IEEE J. Solid State Circuits, 2004