Yun-Shiang Shu

According to our database1, Yun-Shiang Shu authored at least 17 papers between 2008 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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On csauthors.net:

Bibliography

2021
F2: Pushing the Frontiers in Accuracy for Data Converters and Analog Circuits.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
9.1 A Current-Sensing Front-End Realized by A Continuous-Time Incremental ADC with 12b SAR Quantizer and Reset-Then-Open Resistive DAC Achieving 140dB DR and 8ppm INL at 4kS/s.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

26.1 A 4.5mm<sup>2</sup> Multimodal Biosensing SoC for PPG, ECG, BIOZ and GSR Acquisition in Consumer Wearable Devices.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
An Amplifier-Less Calibration-Free SAR ADC Achieving >100dB SNDR for Multi-Channel ECG Acquisition with 667mVpp Linear Input Range.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2016
An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS.
IEEE J. Solid State Circuits, 2016

27.2 an oversampling SAR ADC with DAC mismatch error shaping achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A 1V 9pA analog front end with compressed sensing for electrocardiogram monitoring.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2013
A background calibration technique for fully dynamic flash ADCs.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A 28fJ/conv-step CT ΔΣ modulator with 78dB DR and 18MHz BW in 28nm CMOS using a highly digital multibit quantizer.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators.
Proceedings of the Symposium on VLSI Circuits, 2012

2010
LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time Delta Sigma Modulators.
IEEE J. Solid State Circuits, 2010

2009
A 10∼15-bit 60-MS/s Floating-Point ADC With Digital Gain and Offset Calibration.
IEEE J. Solid State Circuits, 2009

A self-calibrated 2-1-1 cascaded continuous-time ΔΣ modulator.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
A 15-bit Linear 20-MS/s Pipelined ADC Digitally Calibrated With Signal-Dependent Dithering.
IEEE J. Solid State Circuits, 2008

A 65nm CMOS CT ΔΣ Modulator with 81dB DR and 8MHz BW Auto-Tuned by Pulse Injection.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 10∼15b 60MS/s floating-point ADC with digital gain and offset calibration.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008


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