Yusuke Niki

According to our database, Yusuke Niki authored at least 7 papers between 2010 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit.

Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa

IEEE J. Solid State Circuits, 2014

2013

A supply-noise-rejection technique in ADPLL with noise-cancelling current source.

Yusuke Niki, Daisuke Miyashita, Hiroyuki Kobayashi, Shouhei Kousai

Proceedings of the ESSCIRC 2013, 2013

2012

A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs.

Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe

Proceedings of the Symposium on VLSI Circuits, 2012

Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction.

Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

2011

A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers.

Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe

IEEE J. Solid State Circuits, 2011

A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access.

Keiichi Kushida, Osamu Hirabayashi, Fumihiko Tachibana, Hiroyuki Hara, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Yuki Fujimura, Yusuke Niki, Miyako Shizuno, Shinichi Sasaki, Tomoaki Yabe

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm² cell in 32nm high-k metal-gate CMOS.

Yuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki, Azuma Suzuki, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Gou Fukano, Akira Katayama, Yusuke Niki, Tomoaki Yabe

Proceedings of the IEEE International Solid-State Circuits Conference, 2010