Atsushi Kawasumi

According to our database, Atsushi Kawasumi authored at least 28 papers between 2002 and 2020.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2020

Introduction to the Special Section on the 2019 Asian Solid-State Circuits Conference (A-SSCC).

Atsushi Kawasumi, Mototsugu Hamada, Po-Hung Chen

IEEE J. Solid State Circuits, 2020

2017

Introduction to the January Special Issue on the 2016 IEEE International Solid-State Circuits Conference.

Dennis Sylvester, Dejan Markovic, Roman Genov, Atsushi Kawasumi, Subhasish Mitra

IEEE J. Solid State Circuits, 2017

2016

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme.

Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Session 17 overview: SRAM.

Hugh Mair, Atsushi Kawasumi

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture.

Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit.

Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa

IEEE J. Solid State Circuits, 2014

2013

Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges.

Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara

IEEE J. Solid State Circuits, 2013

Session 18 overview: Advanced embedded SRAM.

Michael Clinton, Atsushi Kawasumi

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges.

Shinichi Moriwaki, Yasuhiro Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Shinji Miyano, Takayasu Sakurai, Hirofumi Shinohara

Proceedings of the Symposium on VLSI Circuits, 2012

A 47% access time reduction with a worst-case timing-generation scheme utilizing a statistical method for ultra low voltage SRAMs.

Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe

Proceedings of the Symposium on VLSI Circuits, 2012

A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme.

Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction.

Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations.

Yasue Yamamoto, Atsushi Kawasumi, Shinichi Moriwaki, Toshikazu Suzuki, Shinji Miyano, Hirofumi Shinohara

Proceedings of the 38th European Solid-State Circuit conference, 2012

2011

Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits.

Yu Pu, Xin Zhang, Katsuyuki Ikeuchi, Atsushi Muramatsu, Atsushi Kawasumi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers.

Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe

IEEE J. Solid State Circuits, 2011

0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme.

Shinichi Moriwaki, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Shinji Miyano

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

A trimless, 0.5V-1.0V wide voltage operation, high density SRAM macro utilizing dynamic cell stability monitor and multiple memory cell access.

Keiichi Kushida, Osamu Hirabayashi, Fumihiko Tachibana, Hiroyuki Hara, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Yuki Fujimura, Yusuke Niki, Miyako Shizuno, Shinichi Sasaki, Tomoaki Yabe

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme.

Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010

A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers.

Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Yuki Fujimura, Tomoaki Yabe

IEEE J. Solid State Circuits, 2010

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm² cell in 32nm high-k metal-gate CMOS.

Yuki Fujimura, Osamu Hirabayashi, Takahiko Sasaki, Azuma Suzuki, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Gou Fukano, Akira Katayama, Yusuke Niki, Tomoaki Yabe

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme.

Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009

A 0.7 V Single-Supply SRAM With 0.495 µm² Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme.

Keiichi Kushida, Azuma Suzuki, Gou Fukano, Atsushi Kawasumi, Osamu Hirabayashi, Yasuhisa Takeyama, Takahiko Sasaki, Akira Katayama, Yuki Fujimura, Tomoaki Yabe

IEEE J. Solid State Circuits, 2009

A process-variation-tolerant dual-power-supply SRAM with 0.179µm² Cell in 40nm CMOS using level-programmable wordline driver.

Osamu Hirabayashi, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Keiichi Kushida, Takahiko Sasaki, Akira Katayama, Gou Fukano, Yuki Fujimura, Takaaki Nakazato, Yasushi Shizuki, Natsuki Kushiyama, Tomoaki Yabe

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-×-ratio Memory Cell.

Atsushi Kawasumi, Tomoaki Yabe, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Akihito Tohata, Takahiko Sasaki, Akira Katayama, Gou Fukano, Yuki Fujimura, Nobuaki Otsuka

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI.

Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata

IBM J. Res. Dev., 2007

2005

Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor.

Toru Asano, Joel Silberman, Sang H. Dhong, Osamu Takahashi, Michael White, Scott R. Cottier, Takaaki Nakazato, Atsushi Kawasumi, Hiroshi Yoshihara

IEEE Micro, 2005

The circuit design of the synergistic processor element of a CELL processor.

Osamu Takahashi, Russ Cook, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Hwa-Joon Oh, S. Onish, Juergen Pille, Joel Silberman

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2002

DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs.

Osamu Hirabayashi, Azuma Suzuki, Tomoaki Yabe, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Akihito Tohata, Nobuaki Otsuka

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002