Yasuo Unekawa

According to our database, Yasuo Unekawa authored at least 16 papers between 2001 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2018

An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer.

Shusuke Kawai, Hiromitsu Aoyama, Rui Ito, Yutaka Shimizu, Mitsuyuki Ashida, Asuka Maki, Tomohiko Takeuchi, Hiroyuki Kobayashi, Go Urakawa, Hiroaki Hoshino, Shigehito Saigusa, Kazushi Koyama, Makoto Morita, Ryuichi Nihei, Daisuke Goto, Motoki Nagata, Kengo Nakata, Katsuyuki Ikeuchi, Kentaro Yoshioka, Ryoichi Tachibana, Makoto Arai, Chen Kong Teh, Atsushi Suzuki, Hiroshi Yoshida, Yosuke Hagiwara, Takayuki Kato, Ichiro Seto, Tomoya Horiguchi, Koichiro Ban, Kyosuke Takahashi, Hirotsugu Kajihara, Toshiyuki Yamagishi, Yuki Fujimura, Kazuhisa Horiuchi, Katsuya Nonin, Kengo Kurose, Hideki Yamada, Kentaro Taniguchi, Masahiro Sekiya, Takeshi Tomizawa, Daisuke Taki, Masaaki Ikuta, Tomoya Suzuki, Yuki Ando, Daisuke Yashima, Takahisa Kaihotsu, Hiroki Mori, Kensuke Nakanishi, Takeshi Kumagaya, Yasuo Unekawa, Tsuguhide Aoki, Kohei Onizuka, Toshiya Mitomo

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2014

A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit.

Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa

IEEE J. Solid State Circuits, 2014

An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing.

Daisuke Miyashita, Ryo Yamaki, Kazunori Hashiyoshi, Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa

IEEE J. Solid State Circuits, 2014

3D-integrated, low-height, small module design techniques for 4.48GHz, 560MHz-bandwidth TransferJet™ transceiver.

Kenichi Agawa, Ichiro Seto, Akihiko Happoya, Yoshihiro Iida, Yusuke Imaizumi, Motochika Okano, Daigo Suzuki, Yuichi Sato, Masaomi Iwanaga, Kazumi Sato, Satoshi Arai, Noriaki Uchida, Koji Ryugo, Daisuke Miyashita, Ryuichi Fujimoto, Yasuo Unekawa

Proceedings of the 2014 IEEE Radio and Wireless Symposium, 2014

19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension.

Konosuke Watanabe, Kenichiro Yoshii, Nobuhiro Kondo, Ken-ichi Maeda, Toshio Fujisawa, Junji Wadatsumi, Daisuke Miyashita, Shouhei Kousai, Yasuo Unekawa, Shinsuke Fujii, Takuma Aoyama, Takayuki Tamura, Atsushi Kunimatsu, Yukihito Oowaki

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

4.1 A 3-phase digitally controlled DC-DC converter with 88% ripple reduced 1-cycle phase adding/dropping scheme and 28% power saving CT/DT hybrid current control.

Chen Kong Teh, Atsushi Suzuki, Manabu Yamada, Mototsugu Hamada, Yasuo Unekawa

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

A Standard-Cell Based On-Chip NMOS and PMOS Performance Monitor for Process Variability Compensation.

Toshiyuki Yamagishi, Tatsuo Shiozawa, Koji Horisaki, Hiroyuki Hara, Yasuo Unekawa

IEICE Trans. Electron., 2013

A -70 dBm-Sensitivity 522 Mbps 0.19 nJ/bit-TX 0.43 nJ/bit-RX Transceiver for TransferJet^TM SoC in 65 nm CMOS.

Daisuke Miyashita, Kenichi Agawa, Hirotsugu Kajihara, Kenichi Sami, Ichiro Seto, Ryuichi Fujimoto, Yasuo Unekawa

IEICE Trans. Electron., 2013

A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing.

Daisuke Miyashita, Ryo Yamaki, Kazunori Hashiyoshi, Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS.

Daisuke Miyashita, Kenichi Agawa, Hirotsugu Kajihara, Kenichi Sami, Masaomi Iwanaga, Yosuke Ogasawara, Tomohiko Ito, Daisuke Kurose, Naotaka Koide, Toru Hashimoto, Hiroki Sakurai, Takafumi Yamaji, Takashi Kurihara, Kazumi Sato, Ichiro Seto, Hiroshi Yoshida, Ryuichi Fujimoto, Yasuo Unekawa

Proceedings of the Symposium on VLSI Circuits, 2012

An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation.

Toshiyuki Yamagishi, Tatsuo Shiozawa, Koji Horisaki, Hiroyuki Hara, Yasuo Unekawa

Proceedings of the 2012 IEEE Symposium on Low-Power and High-Speed Chips, 2012

2011

High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors.

Tomoya Suzuki, Hideki Yamada, Toshiyuki Yamagishi, Daisuke Takeda, Koji Horisaki, Tom Vander Aa, Toshio Fujisawa, Liesbet Van der Perre, Yasuo Unekawa

IEEE Micro, 2011

A multimodal wireless baseband core using a coarse-grained dynamic reconfigurable processor.

Hideki Yamada, Toshiyuki Yamagishi, Tomoya Suzuki, Kuniaki Ito, Koji Horisaki, Tom Vander Aa, Toshio Fujisawa, Liesbet Van der Perre, Yasuo Unekawa

Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications.

Daisuke Taki, Tatsuo Shiozawa, Kuniaki Ito, Youichiro Shiba, Kouji Horisaki, Hirotsugu Kajihara, Toshiyuki Yamagishi, Masahiro Sekiya, Akira Yamaga, Tetsuya Fujita, Hiroyuki Hara, Masanori Kuwahara, Toshio Fujisawa, Yasuo Unekawa

Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

2003

A single-chip 802.11a MAC/PHY with a 32-b RISC processor.

Toshio Fujisawa, Jun Hasegawa, Koji Tsuchie, Tatsuo Shiozawa, Tetsuya Fujita, Toshitada Saito, Yasuo Unekawa

IEEE J. Solid State Circuits, 2003

2001

Shared data line technique for doubling the data transfer rate per pin of differential interfaces.

Fumitoshi Hatori, Shouhei Kousai, Yasuo Unekawa

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001