Shouhei Kousai
According to our database1,
Shouhei Kousai
authored at least 35 papers
between 2001 and 2017.
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Bibliography
2017
A Neuromorphic Chip Optimized for Deep Learning and CMOS Technology With Time-Domain Analog and Digital Mixed-Signal Processing.
IEEE J. Solid State Circuits, 2017
A Compact Broadband Mixed-Signal Power Amplifier in Bulk CMOS With Hybrid Class-G and Dynamic Load Trajectory Manipulation.
IEEE J. Solid State Circuits, 2017
2016
A Broadband Mixed-Signal CMOS Power Amplifier With a Hybrid Class-G Doherty Efficiency Enhancement Technique.
IEEE J. Solid State Circuits, 2016
Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
Design of A Transformer-Based Reconfigurable Digital Polar Doherty Power Amplifier Fully Integrated in Bulk CMOS.
IEEE J. Solid State Circuits, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2.8 A broadband CMOS digital power amplifier with hybrid Class-G Doherty efficiency enhancement.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
IEEE J. Solid State Circuits, 2014
Polar Antenna Impedance Detection and Tuning for Efficiency Improvement in a 3G/4G CMOS Power Amplifier.
IEEE J. Solid State Circuits, 2014
A 2.9mW, +/- 85ppm accuracy reference clock generator based on RC oscillator with on-chip temperature calibration.
Proceedings of the Symposium on VLSI Circuits, 2014
19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
3.1 polar antenna impedance detection and tuning for efficiency improvement in a 3G/4G CMOS Power Amplifier.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A new wave of CMOS power amplifier innovations: Fusing digital and analog techniques with large signal RF operations.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
A 1.4Mpixel CMOS image sensor with multiple row-rescan based data sampling for optical camera communication.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the ESSCIRC 2013, 2013
A fully differential ultra-compact broadband transformer based quadrature generation scheme.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
A 28.3 mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a + 27.1 dBm WCDMA CMOS Power Amplifier.
IEEE J. Solid State Circuits, 2012
A-104 dBc/Hz In-Band Phase Noise 3 GHz All Digital PLL with Phase Interpolation Based Hierarchical Time to Digital Converter.
IEICE Trans. Electron., 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 28.3mW PA-closed loop for linearity and efficiency improvement integrated in a +27.1dBm WCDMA CMOS power amplifier.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
A Low-Noise and Highly-Linear Transmitter with Envelope Injection Pre-Power Amplifier for Multi-Mode Radio.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
An all-digital 8-DPSK polar transmitter with second-order approximation scheme and phase rotation-constant digital PA for bluetooth EDR in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2009
An Octave-Range, Watt-Level, Fully-Integrated CMOS Switching Power Mixer Array for Linearization and Back-Off-Efficiency Improvement.
IEEE J. Solid State Circuits, 2009
A Novel Automatic Quality Factor Tuning Scheme for a Low-Power Wideband Active-RC Filter.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
2008
A 1.2V 0.2-to-6.3GHz Transceiver with Less Than -29.5dB EVM@-3dBm and a Choke/Coil-Less Pre-Power Amplifier.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
A 19.7 MHz, Fifth-Order Active-RCChebyshev LPF for Draft IEEE802.11n With Automatic Quality-Factor Tuning Scheme.
IEEE J. Solid State Circuits, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2005
A 2.4-GHz Temperature-Compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitters.
IEICE Trans. Electron., 2005
A phase noise minimization of CMOS VCOs over wide tuning range and large PVT variations.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
A temperature-compensated CMOS LC-VCO enabling the direct modulation architecture in 2.4GHz GFSK transmitter.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2001
Shared data line technique for doubling the data transfer rate per pin of differential interfaces.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001