Zhenyu Sun

According to our database, Zhenyu Sun authored at least 15 papers between 2010 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

Array Organization and Data Management Exploration in Racetrack Memory.

Zhenyu Sun, Xiuyuan Bi, Wenqing Wu, Sungjoo Yoo, Hai (Helen) Li

IEEE Trans. Computers, 2016

Spintronic Memristor as Interface Between DNA and Solid State Devices.

Jianlei Yang, Zhenyu Sun, Xiaobin Wang, Yiran Chen, Hai Li

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

2015

Read Performance: The Newest Barrier in Scaled STT-RAM.

Yaojun Zhang, Yong Li, Zhenyu Sun, Hai Li, Yiran Chen, Alex K. Jones

IEEE Trans. Very Large Scale Integr. Syst., 2015

The evolutionary spintronic technologies and their usage in high performance computing.

Hai (Helen) Li, Xiuyuan Bi, Zhenyu Sun

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

2014

STT-RAM Cache Hierarchy With Multiretention MTJ Designs.

Zhenyu Sun, Xiuyuan Bi, Hai Li, Weng-Fai Wong, Xiaochun Zhu

IEEE Trans. Very Large Scale Integr. Syst., 2014

Design exploration of racetrack lower-level caches.

Zhenyu Sun, Xiuyuan Bi, Alex K. Jones, Hai Li

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores.

Jianxing Wang, Yenni Tim, Weng-Fai Wong, Zhong-Liang Ong, Zhenyu Sun, Hai Li

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Cross-layer racetrack memory design for ultra high density and low power consumption.

Zhenyu Sun, Wenqing Wu, Hai (Helen) Li

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Voltage Driven Nondestructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory.

Zhenyu Sun, Hai Li, Yiran Chen, Xiaobin Wang

IEEE Trans. Very Large Scale Integr. Syst., 2012

Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder.

Zhenyu Sun, Xiang Chen, Yaojun Zhang, Hai Li, Yiran Chen

ACM J. Emerg. Technol. Comput. Syst., 2012

A dual-mode architecture for fast-switching STT-RAM.

Zhenyu Sun, Hai Li, Wenqing Wu

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Process variation aware data management for STT-RAM cache design.

Zhenyu Sun, Xiuyuan Bi, Hai Li

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches.

Xiuyuan Bi, Zhenyu Sun, Hai Li, Wenqing Wu

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011

Multi retention level STT-RAM cache designs with a dynamic refresh scheme.

Zhenyu Sun, Xiuyuan Bi, Hai (Helen) Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu

Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

2010

Variation tolerant sensing scheme of Spin-Transfer Torque Memory for yield improvement.

Zhenyu Sun, Hai Li, Yiran Chen, Xiaobin Wang

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010