Xiuyuan Bi

According to our database, Xiuyuan Bi authored at least 17 papers between 2011 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Exploring Applications of STT-RAM in GPU Architectures.

Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Helen Li, Yiran Chen

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2017

Cross-Layer Optimization for Multilevel Cell STT-RAM Caches.

Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Helen Li

IEEE Trans. Very Large Scale Integr. Syst., 2017

2016

Array Organization and Data Management Exploration in Racetrack Memory.

Zhenyu Sun, Xiuyuan Bi, Wenqing Wu, Sungjoo Yoo, Hai (Helen) Li

IEEE Trans. Computers, 2016

Design and Implementation of a 4Kb STT-MRAM with Innovative 200nm Nano-ring Shaped MTJ.

Zheng Li, Xiuyuan Bi, Hai (Helen) Li, Yiran Chen, Jianying Qin, Peng Guo, Wenjie Kong, Wenshan Zhan, Xiufeng Han, Hong Zhang, Lingling Wang, Guanping Wu, Hanming Wu

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

2015

The evolutionary spintronic technologies and their usage in high performance computing.

Hai (Helen) Li, Xiuyuan Bi, Zhenyu Sun

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

An efficient STT-RAM-based register file in GPU architectures.

Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Li, Yiran Chen

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

STT-RAM Cache Hierarchy With Multiretention MTJ Designs.

Zhenyu Sun, Xiuyuan Bi, Hai Li, Weng-Fai Wong, Xiaochun Zhu

IEEE Trans. Very Large Scale Integr. Syst., 2014

Design exploration of racetrack lower-level caches.

Zhenyu Sun, Xiuyuan Bi, Alex K. Jones, Hai Li

Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Optimizing MLC-based STT-RAM caches by dynamic block size reconfiguration.

Jianxing Wang, Pooja Roy, Weng-Fai Wong, Xiuyuan Bi, Hai Li

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

A pseudo-weighted sensing scheme for memristor based cross-point memory.

Zhijie Chen, Lu Zhang, Xiuyuan Bi, Hai Li

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Unleashing the potential of MLC STT-RAM caches.

Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Li

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

STT-RAM designs supporting dual-port accesses.

Xiuyuan Bi, Mohamed Anis Weldon, Hai Li

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design.

Xiuyuan Bi, Hai Li, Jae-Joon Kim

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Process variation aware data management for STT-RAM cache design.

Zhenyu Sun, Xiuyuan Bi, Hai Li

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches.

Xiuyuan Bi, Zhenyu Sun, Hai Li, Wenqing Wu

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Spintronic memristor based temperature sensor design with CMOS current reference.

Xiuyuan Bi, Chao Zhang, Hai Li, Yiran Chen, Robinson E. Pino

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Multi retention level STT-RAM cache designs with a dynamic refresh scheme.

Zhenyu Sun, Xiuyuan Bi, Hai (Helen) Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu

Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011