Yaojun Zhang

Orcid: 0000-0002-0125-2221

According to our database¹, Yaojun Zhang authored at least 42 papers between 2009 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2023

Exploring the Relationships between Land Surface Temperature and Its Influencing Factors Using Multisource Spatial Big Data: A Case Study in Beijing, China.

[BibT_eX]

[DOI]

Xiaoxi Wang

Yaojun Zhang

Danlin Yu

Remote. Sens., April, 2023

Hadamard product-based in-memory computing design for floating point neural network training.

[BibT_eX]

[DOI]

Neuromorph. Comput. Eng., March, 2023

Bayesian CART models for insurance claims frequency.

[BibT_eX]

[DOI]

CoRR, 2023

SRAM-Based Processing-In-Memory Design with Kullback-Leibler Divergence-Based Dynamic Precision Quantization.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Live Demonstration: SRAM Compute-In-Memory Based Visual & Aural Recognition System.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

A 1.041-Mb/mm<sup>2</sup> 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Heterogeneous Memory Architecture Accommodating Processing-in-Memory on SoC for AIoT Applications.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Stock Market Prediction Model Based on LSTM Deep Learning: The Case of Top Corporate Company in China.

[BibT_eX]

[DOI]

Yaojun Zhang

Gilbert M. Tumibay

Proceedings of the 4th International Conference on Artificial Intelligence and Advanced Manufacturing, 2022

2018

Exploring the opportunity of implementing neuromorphic computing systems with spintronic devices.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

Giant Spin-Hall assisted STT-RAM and logic design.

[BibT_eX]

[DOI]

Integr., 2017

2016

Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Spin-Hall Assisted STT-RAM Design and Discussion.

[BibT_eX]

[DOI]

Proceedings of the 18th System Level Interconnect Prediction Workshop, 2016

A novel PUF based on cell error rate distribution of STT-RAM.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Read Performance: The Newest Barrier in Scaled STT-RAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback.

[BibT_eX]

[DOI]

Pierre Chor-Fung Chia

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Giant spin hall effect (GSHE) logic design for low power application.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Recent progresses of STT memory design and applications.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

State-Restrict MLC STT-RAM Designs for High-Reliable High-Performance Memory System.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architectures.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

C1C: A configurable, compiler-guided STT-RAM L1 cache.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2013

On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2013

MLC STT-RAM design considering probabilistic and asymmetric MTJ switching.

[BibT_eX]

[DOI]

Yaojun Zhang

Lu Zhang

Yiran Chen

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Pseudo-Three-Dimensional Navigation in Helical Scan Security Inspection.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Conference on Image and Graphics, 2013

ADAMS: asymmetric differential STT-RAM cell structure for reliable and high-performance applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

DA-RAID-5: a disturb aware data protection technique for NAND flash storage systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Loadsa: A yield-driven top-down design method for STT-RAM array.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Nonvolatile Memories as the Data Storage System for Implantable ECG Recorder.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2012

Combating Write Penalties Using Software Dispatch for On-Chip MRAM Integration.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2012

iFeel6-BH1500: A large-scale 6-DOF haptic device.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Conference on Virtual Environments Human-Computer Interfaces and Measurement Systems, 2012

Improving energy efficiency of write-asymmetric memories by log style write.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Multi-level cell STT-RAM: Is it realistic or just a dream?

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Asymmetry of MTJ switching and its implication to STT-RAM designs.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Probabilistic design in spintronic memory and logic circuit.

[BibT_eX]

[DOI]

Yiran Chen

Yaojun Zhang

Peiyuan Wang

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view.

[BibT_eX]

[DOI]

Yaojun Zhang

Xiaobin Wang

Yiran Chen

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

The analysis of resolution for cable-driven haptic device.

[BibT_eX]

[DOI]

Proceedings of the 2010 IEEE International Conference on Robotics and Biomimetics, 2010

2009

Workspace analysis of a novel 6-dof cable-driven parallel robot.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2009

Yaojun Zhang

Timeline

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On csauthors.net:

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