Xiaochun Zhu

Orcid: 0000-0002-2485-5973

According to our database1, Xiaochun Zhu authored at least 24 papers between 1991 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Monitoring the Production Information of Conventional Machining Equipment Based on Edge Computing.
Sensors, 2023

Robust Stereo Road Image Segmentation Using Threshold Selection Optimization Method Based on Persistent Homology.
IEEE Access, 2023

Enhanced A* Path Planning Algorithm Integrating Bezier Curves for Application in Mobile Robots.
Proceedings of the 6th International Conference on Information Technologies and Electrical Engineering, 2023

Overcoming Occlusion for Robust Facial Expression Recognition using Adaptive Dual-Attention Net.
Proceedings of the 6th International Conference on Information Technologies and Electrical Engineering, 2023

2022
Development of equipment production information monitoring system based on electric current signal.
Proceedings of the 3rd International Conference on Computing, 2022

2021
Water Extraction Method Based on Multi-Texture Feature Fusion of Synthetic Aperture Radar Images.
Sensors, 2021

Output feedback stabilization via nonlinear mapping for time-varying constrained nonholonomic systems in prescribed finite time.
Inf. Sci., 2021

2020
Nonlinear mapping-based fixed-time stabilization of uncertain nonholonomic systems with time-varying state constraints.
J. Frankl. Inst., 2020

Design and Production of a New Console Training Platform.
Proceedings of the Cyber Security Intelligence and Analytics, 2020

2017
Simulation research on rear active steering-based 4WIS electric vehicle steering control.
Proceedings of the 24th International Conference on Mechatronics and Machine Vision in Practice, 2017

2015
Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach.
IEEE Trans. Multi Scale Comput. Syst., 2015

2014
STT-RAM Cache Hierarchy With Multiretention MTJ Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

2013
CD-ECC: content-dependent error correction codes for combating asymmetric nonvolatile memory operation errors.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012
Probabilistically Programmed STT-MRAM.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

2011
Multi retention level STT-RAM cache designs with a dynamic refresh scheme.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

Device-architecture co-optimization of STT-RAM based memory for low power embedded systems.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A 1.0V 45nm nonvolatile magnetic latch design and its robustness analysis.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2009
Software testing sizing in incremental development: A case study.
Proceedings of the Third International Symposium on Empirical Software Engineering and Measurement, 2009

Simulation of the defect removal process with queuing theory.
Proceedings of the Third International Symposium on Empirical Software Engineering and Measurement, 2009

2008
An Experience-Based Approach for Test Execution Effort Estimation.
Proceedings of the 9th International Conference for Young Computer Scientists, 2008

Estimate Test Execution Effort at an Early Stage: An Empirical Study.
Proceedings of the International Conference on Cyberworlds 2008, 2008

Early Estimate the Size of Test Suites from Use Cases.
Proceedings of the 15th Asia-Pacific Software Engineering Conference (APSEC 2008), 2008

1991
A Simulating System for NC Lathe.
Proceedings of the Information Technology for Advanced Manufacturing Systems, 1991


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