Liang Fang

Orcid: 0000-0003-3498-3685

Affiliations:
  • National Key Laboratory for High Performance Computing, Changsha, Hunan, China


According to our database1, Liang Fang authored at least 10 papers between 2020 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2025
ILOSSS - Improved Logic Synthesis based on Several Stateful Logic Gates.
ACM Trans. Design Autom. Electr. Syst., July, 2025

2024
LOSSS-Logic Synthesis based on Several Stateful logic gates for high time-efficient computing.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
AIMCU-MESO: An In-Memory Computing Unit Constructed by MESO Device.
ACM Trans. Design Autom. Electr. Syst., January, 2023

Rescuing ReRAM-based Neural Computing Systems from Device Variation.
ACM Trans. Design Autom. Electr. Syst., January, 2023

2022
A 625kHz-BW, 79.3dB-SNDR Second-Order Noise-Shaping SAR ADC Using High-Efficiency Error-Feedback Structure.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

MESO-LUT: A design approach of look up tables based on MESO devices.
Microelectron. J., 2022

2021
HDNH: a read-efficient and write-optimized hashing scheme for hybrid DRAM-NVM memory.
Proceedings of the ICPP 2021: 50th International Conference on Parallel Processing, Lemont, IL, USA, August 9, 2021

Simulation of serial RRAM cell based on a Verilog-A compact model.
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

2020
A forming-free ReRAM cell with low operating voltage.
IEICE Electron. Express, 2020

A Stateful Logic Family Based on a New Logic Primitive Circuit Composed of Two Antiparallel Bipolar Memristors.
Adv. Intell. Syst., 2020


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