Zhiying Wang

According to our database1, Zhiying Wang
  • authored at least 255 papers between 1990 and 2018.
  • has a "Dijkstra number"2 of three.

Timeline

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Bibliography

2018
Storage-Efficient Shared Memory Emulation.
CoRR, 2018

Wireless MapReduce Distributed Computing.
CoRR, 2018

On the Achievability Region of Regenerating Codes for Multiple Erasures.
CoRR, 2018

The Asymptotic Capacity of Private Search.
CoRR, 2018

ChIPWig: a random access-enabling lossless and lossy compression method for ChIP-seq data.
Bioinformatics, 2018

2017
Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip.
IEEE Trans. VLSI Syst., 2017

Optimal Rebuilding of Multiple Erasures in MDS Codes.
IEEE Trans. Information Theory, 2017

Switch Codes: Codes for Fully Parallel Reconstruction.
IEEE Trans. Information Theory, 2017

Improving the Efficiency of GPGPU Work-Queue Through Data Awareness.
TACO, 2017

UTrustDisk: An Efficient Data Protection Scheme for Building Trusted USB Flash Disk.
TIIS, 2017

A high performance reliable NoC router.
Integration, 2017

Understanding co-run performance on CPU-GPU integrated processors: observations, insights, directions.
Frontiers Comput. Sci., 2017

Learning general model for activity recognition with limited labelled data.
Expert Syst. Appl., 2017

The Capacity of Private Information Retrieval with Private Side Information.
CoRR, 2017

Centralized Multi-Node Repair Regenerating Codes.
CoRR, 2017

Efficient and high-quality sparse graph coloring on GPUs.
Concurrency and Computation: Practice and Experience, 2017

Factor-Based C-AMAT Analysis for Memory Optimization.
Proceedings of the Verification and Evaluation of Computer and Communication Systems, 2017

Runtime Measurement Architecture for Bytecode Integrity in JVM-Based Cloud.
Proceedings of the 36th IEEE Symposium on Reliable Distributed Systems, 2017

Decoupling Security Services from IaaS Cloud Through Remote Virtual Machine Introspection.
Proceedings of the Security, Privacy, and Anonymity in Computation, Communication, and Storage, 2017

A Novel Approach to Reduce Packet Latency Increase Caused by Power Gating in Network-on-Chip.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Unleashing the power of GPU for physically-based rendering via dynamic ray shuffling.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Centralized multi-node repair for minimum storage regenerating codes.
Proceedings of the 2017 IEEE International Symposium on Information Theory, 2017

Rate-compatible and high-throughput architecture designs for encoding LDPC codes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Co-Run Scheduling with Power Cap on Integrated CPU-GPU Systems.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

A Novel Statistical Power Model for Integrated GPU with Optimization.
Proceedings of the Data Science, 2017

Efficient CP-ABE with Non-monotonic Access Structures.
Proceedings of the Cloud Computing and Security - Third International Conference, 2017

Trace-based method for big data memory characteristics research.
Proceedings of the 2017 International Conference on Advances in Computing, 2017

BC-AMAT: Considering Blocked Time in Memory System Measurement.
Proceedings of the Computing Frontiers Conference, 2017

A tradeoff between the sub-packetization size and the repair bandwidth for reed-solomon code.
Proceedings of the 55th Annual Allerton Conference on Communication, 2017

A Software-Hardware Co-designed Methodology for Efficient Thread Level Speculation.
Proceedings of the 2017 IEEE International Conference on Computer and Information Technology, 2017

2016
Explicit Minimum Storage Regenerating Codes.
IEEE Trans. Information Theory, 2016

Dual arm-angle parameterisation and its applications for analytical inverse kinematics of redundant manipulators.
Robotica, 2016

A runtime fault-tolerant routing algorithm based on region flooding in NoCs.
Microprocessors and Microsystems - Embedded Hardware Design, 2016

Optimization Strategies Oriented to Loop Characteristics in Software Thread Level Speculation Systems.
J. Comput. Sci. Technol., 2016

Differentiated management strategies on cloud computing data security driven by data value.
Information Security Journal: A Global Perspective, 2016

Sensor-based adaptive activity recognition with dynamically available sensors.
Neurocomputing, 2016

User-policy-based dynamic remote attestation in cloud computing.
IJES, 2016

Optimal Rebuilding of Multiple Erasures in MDS Codes.
CoRR, 2016

Information-Theoretic Lower Bounds on the Storage Cost of Shared Memory Emulation.
CoRR, 2016

smallWig: parallel compression of RNA-seq WIG files.
Bioinformatics, 2016

Information-Theoretic Lower Bounds on the Storage Cost of Shared Memory Emulation.
Proceedings of the 2016 ACM Symposium on Principles of Distributed Computing, 2016

Dynamic Power-Performance Adjustment on Clustered Multi-Threading Processors.
Proceedings of the IEEE International Conference on Networking, 2016

An implementation of analytical power model on integrated GPU.
Proceedings of the International Symposium on Integrated Circuits, 2016

A heterogeneous low-cost and low-latency Ring-Chain network for GPGPUs.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

OBC Based Optimization of Re-encryption for Cryptographic Cloud Storage.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2016

A Hybrid Power-Performance Adjustment Strategy for Clustered Multi-threading Architecture.
Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016

A low-cost conflict-free NoC for GPGPUs.
Proceedings of the 53rd Annual Design Automation Conference, 2016

A high performance reliable NoC router.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Centralized multi-node repair in distributed storage.
Proceedings of the 54th Annual Allerton Conference on Communication, 2016

2015
Leaving One Slot Empty: Flit Bubble Flow Control for Torus Cache-Coherent NoCs.
IEEE Trans. Computers, 2015

Activity recognition with weighted frequent patterns mining in smart environments.
Expert Syst. Appl., 2015

Multi-Version Coding in Distributed Storage.
CoRR, 2015

Adaptive Cache and Concurrency Allocation on GPGPUs.
Computer Architecture Letters, 2015

Optimal binary switch codes with small query size.
Proceedings of the IEEE International Symposium on Information Theory, 2015

A practical and effective method for identifying the complete inertia parameters of space robots.
Proceedings of the 2015 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2015

Efficient data management on 3D stacked memory for big data applications.
Proceedings of the 10th International Design & Test Symposium, 2015

A Study on Non-volatile 3D Stacked Memory for Big Data Applications.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

Application-Assisted Dynamic Attestation for JVM-Based Cloud.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

Software Engagement with Sleeping CPUs.
Proceedings of the 15th Workshop on Hot Topics in Operating Systems, 2015

Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Adaptive remaining hop count flow control: Consider the interaction between packets.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Novel Flow Control for Fully Adaptive Routing in Cache-Coherent NoCs.
IEEE Trans. Parallel Distrib. Syst., 2014

Integrated Coherence Prediction: Towards Efficient Cache Coherence on NoC-Based Multicore Architectures.
ACM Trans. Design Autom. Electr. Syst., 2014

Access Versus Bandwidth in Codes for Storage.
IEEE Trans. Information Theory, 2014

Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs.
IEEE Trans. Computers, 2014

Collaborative representation with reduced residual for face recognition.
Neural Computing and Applications, 2014

Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes.
Microprocessors and Microsystems - Embedded Hardware Design, 2014

Mac or Non-MAC: not a Problem.
Journal of Circuits, Systems, and Computers, 2014

A comprehensive comparison between virtual cut-through and wormhole routers for cache coherent Network on-Chips.
IEICE Electronic Express, 2014

Explicit MDS Codes for Optimal Repair Bandwidth.
CoRR, 2014

Efficient Utilization of SIMD Engines for General-Purpose Processors.
Comput. J., 2014

Binary compatibility for embedded systems using greedy subgraph mapping.
SCIENCE CHINA Information Sciences, 2014

Implementing a Leading Loads Performance Predictor on Commodity Processors.
Proceedings of the 2014 USENIX Annual Technical Conference, 2014

Discovering Latent Structures for Activity Recognition in Smart Environments.
Proceedings of the 2014 IEEE 11th Intl Conf on Ubiquitous Intelligence and Computing and 2014 IEEE 11th Intl Conf on Autonomic and Trusted Computing and 2014 IEEE 14th Intl Conf on Scalable Computing and Communications and Its Associated Workshops, 2014

JVM-Based Dynamic Attestation in Cloud Computing.
Proceedings of the 13th IEEE International Conference on Trust, 2014

The design, control and experiment of a high payload-weight hexapod robot.
Proceedings of the 2014 IEEE International Conference on Robotics and Biomimetics, 2014

Construction of a Collaborative Value Chain in Cloud Computing Environment.
Proceedings of the 18th Pacific Asia Conference on Information Systems, 2014

PPEP: Online Performance, Power, and Energy Prediction Framework and DVFS Space Exploration.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Adaptive Cache Management for Energy-Efficient GPU Computing.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Understanding Co-run Degradations on Integrated Heterogeneous Processors.
Proceedings of the Languages and Compilers for Parallel Computing, 2014

Tag check elision.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Multi-version coding in distributed storage.
Proceedings of the 2014 IEEE International Symposium on Information Theory, Honolulu, HI, USA, June 29, 2014

Adaptive Cache Bypass and Insertion for Many-core Accelerators.
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014

Improving Speculation Accuracy with Inter-thread Fetching Value Prediction.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2014

An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

On multi-version coding for distributed storage.
Proceedings of the 52nd Annual Allerton Conference on Communication, 2014

Dynamic Power Estimation with Hardware Performance Counters Support on Multi-core Platform.
Proceedings of the Advanced Computer Architecture - 10th Annual Conference, 2014

Customized Core Layout: A Case Study on Dual-Core Dynamic Binary Translation System.
Proceedings of the 14th IEEE International Conference on Computer and Information Technology, 2014

2013
Zigzag Codes: MDS Array Codes With Optimal Rebuilding.
IEEE Trans. Information Theory, 2013

Dynamic Streamization Model Execution for SIMD Engines on Multicore Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

Adaptive communication mechanism for accelerating MPI functions in NoC-based multicore processors.
TACO, 2013

Efficient multimedia coprocessor with enhanced SIMD engines for exploiting ILP and DLP.
Parallel Computing, 2013

VBON: Toward efficient on-chip networks via hierarchical virtual bus.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Efficient revocation in ciphertext-policy attribute-based encryption based cryptographic cloud storage.
Journal of Zhejiang University - Science C, 2013

Region-Based Way-Partitioning on L1 Data Cache for Low Power.
IEICE Transactions, 2013

Access vs. Bandwidth in Codes for Storage
CoRR, 2013

An accurate and highly-efficient performance evaluation approach based on queuing model for on-chip network.
SCIENCE CHINA Information Sciences, 2013

Dynamic modeling of self-reconfigurable multi-arm space robotic system with variable topology.
Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2013

Singularity analysis for a class of serial manipulators with non-spherical wrists.
Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2013

Gait planning method of a hexapod robot based on the central pattern generators: Simulation and experiment.
Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2013

Inverse kinematics of SSRMS-type manipulators with single joint locked failure.
Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2013

Dynamic analysis of the compounded system formed by dual-arm space robot and the captured target.
Proceedings of the IEEE International Conference on Robotics and Biomimetics, 2013

Codes for network switches.
Proceedings of the 2013 IEEE International Symposium on Information Theory, 2013

HEUSPEC: A Software Speculation Parallel Model.
Proceedings of the 42nd International Conference on Parallel Processing, 2013

DCP: Improving the Throughput of Asynchronous Pipeline by Dual Control Path.
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications & 2013 IEEE International Conference on Embedded and Ubiquitous Computing, 2013

Transient Fault Tolerant QDI Interconnects Using Redundant Check Code.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
An approach to minimizing the interpretation overhead in Dynamic Binary Translation.
The Journal of Supercomputing, 2012

Low-Cost Binary128 Floating-Point FMA Unit Design with SIMD Support.
IEEE Trans. Computers, 2012

Trusted Bytecode Virtual Machine Module: A Novel Method for Dynamic Remote Attestation in Cloud Computing.
Int. J. Computational Intelligence Systems, 2012

Keys Distributing Optimization of CP-ABE Based Access Control in Cryptographic Cloud Storage.
IEICE Transactions, 2012

Backlog Bounds Analysis of Different On-chip Cache Coherence Policies: A Network Calculus-Based Approch.
Proceedings of the 9th International Conference on Ubiquitous Intelligence and Computing and 9th International Conference on Autonomic and Trusted Computing, 2012

HVD-TLS: A Novel Framework of Thread Level Speculation.
Proceedings of the 11th IEEE International Conference on Trust, 2012

Dynamic Optimization on Multi-core Platform.
Proceedings of the 11th IEEE International Conference on Trust, 2012

Long MDS codes for optimal repair bandwidth.
Proceedings of the 2012 IEEE International Symposium on Information Theory, 2012

Access vs. bandwidth in codes for storage.
Proceedings of the 2012 IEEE International Symposium on Information Theory, 2012

Cosmo SkyMed AO projects - 3D reconstruction and stability monitoring of the Three Gorges Dam.
Proceedings of the 2012 IEEE International Geoscience and Remote Sensing Symposium, 2012

The performance of satellite radar remote sensing technology in ground settlement monitoring.
Proceedings of the 2012 IEEE International Geoscience and Remote Sensing Symposium, 2012

A semantic web service composition dynamic detecting method.
Proceedings of the Seventh International Conference on Digital Information Management, 2012

Whole packet forwarding: Efficient design of fully adaptive routing algorithms for networks-on-chip.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Supporting efficient collective communication in NoCs.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

An optimized multicore cache coherence design for exploiting communication locality.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Attributes Union in CP-ABE Algorithm for Large Universe Cryptographic Access Control.
Proceedings of the 2012 Second International Conference on Cloud and Green Computing, 2012

Re-encryption Optimization in CP-ABE Based Cryptographic Cloud Storage.
Proceedings of the 2012 Second International Conference on Cloud and Green Computing, 2012

End-to-End Delay Bounds Analysis of Different On-chip Cache Coherence Policies: A Network Calculus-Based Approch.
Proceedings of the Sixth Asia Modelling Symposium, 2012

Accelerating NoC-Based MPI Primitives via Communication Architecture Customization.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011
A practical low-latency router architecture with wing channel for on-chip network.
Microprocessors and Microsystems - Embedded Hardware Design, 2011

Zigzag Codes: MDS Array Codes with Optimal Rebuilding
CoRR, 2011

On Codes for Optimal Rebuilding Access
CoRR, 2011

MDS Array Codes with Optimal Rebuilding
CoRR, 2011

VerFAT: A Transparent and Efficient Multi-versioning Mechanism for FAT File System.
Proceedings of the IEEE 10th International Conference on Trust, 2011

An Advanced and Effective Literature Search Algorithm Based on Analytic Hierarchy Process.
Proceedings of the IEEE 10th International Conference on Trust, 2011

SWHash: An Efficient Data Integrity Verification Scheme Appropriate for USB Flash Disk.
Proceedings of the IEEE 10th International Conference on Trust, 2011

GSM: An Efficient Code Generation Algorithm for Dynamic Binary Translator.
Proceedings of the Fourth International Symposium on Parallel Architectures, 2011

MDS array codes with optimal rebuilding.
Proceedings of the 2011 IEEE International Symposium on Information Theory Proceedings, 2011

Patterned cells for phase change memories.
Proceedings of the 2011 IEEE International Symposium on Information Theory Proceedings, 2011

DBAR: an efficient routing algorithm to support multiple concurrent applications in networks-on-chip.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

A Formalization of an Emulation Based Co-designed Virtual Machine.
Proceedings of the Fifth International Conference on Innovative Mobile and Internet Services in Ubiquitous Computing, 2011

Subway tunnels identification through Cosmo-SkyMed PSInSAR analysis in Shanghai.
Proceedings of the 2011 IEEE International Geoscience and Remote Sensing Symposium, 2011

Characterizing Fine-Grain Parallelism on Modern Multicore Platform.
Proceedings of the 17th IEEE International Conference on Parallel and Distributed Systems, 2011

A novel file-level continuous data protection mechanism oriented service application.
Proceedings of the ICIMCS 2011, 2011

Mailbook: privacy-protecting social networking via email.
Proceedings of the ICIMCS 2011, 2011

A novel shared-buffer router for network-on-chip based on Hierarchical Bit-line Buffer.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Applying Formal Verification to a Cache Coherence Protocol in TLS.
Proceedings of the UKSim 5th European Symposium on Computer Modeling and Simulation, 2011

A specialized low-cost vectorized loop buffer for embedded processors.
Proceedings of the Design, Automation and Test in Europe, 2011

Analytical Models for Data Dependence Violation Checking in TLS.
Proceedings of the Seventh International Conference on Computational Intelligence and Security, 2011

On codes for optimal rebuilding access.
Proceedings of the 49th Annual Allerton Conference on Communication, 2011

A Novel Chaining Approach to Indirect Control Transfer Instructions.
Proceedings of the Availability, Reliability and Security for Business, Enterprise and Health Information Systems, 2011

2010
An Emulator for Executing IA-32 Applications on ARM-Based Systems.
JCP, 2010

Exploration and implementation of a highly efficient processor element for multimedia and signal processing domains.
IET Computers & Digital Techniques, 2010

Rebuilding for Array Codes in Distributed Storage Systems
CoRR, 2010

Model Driven Iterative Multi-dimensional Parallelization of Multi-task Programs for the Cell BE: A Genetic Algorithm-Based Approach.
Proceedings of the 18th Euromicro Conference on Parallel, 2010

Partial rank modulation for flash memories.
Proceedings of the IEEE International Symposium on Information Theory, 2010

Permutation optimization for SIMD devices.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

DSS: Applying asynchronous techniques to architectures exploiting ILP at compile time.
Proceedings of the 28th International Conference on Computer Design, 2010

SV: Enhancing SIMD Architectures via Combined SIMD-Vector Approach.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2010

SIF: Overcoming the limitations of SIMD devices via implicit permutation.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Virtual Network Embedding for Evolving Networks.
Proceedings of the Global Communications Conference, 2010

A Dynamic Binary Translation Framework Based on Page Fault Mechanism in Linux Kernel.
Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

2009
Optimal subgraph covering for customisable VLIW processors.
IET Computers & Digital Techniques, 2009

A New Description Language for Data-Driven Asynchronous Circuits and its Design Flow.
Proceedings of the 2009 Pacific-Asia Conference on Circuits, Communications and Systems, 2009

Implementation of OpenVG Path and Paint Algorithms on Synchronous Data Triggered Architecture with Optimization.
Proceedings of the International Conference on Networking, Architecture, and Storage, 2009

The Design of Asynchronous Microprocessor Based on Optimized NCL_X Design-Flow.
Proceedings of the International Conference on Networking, Architecture, and Storage, 2009

Virtual Disk Image Reclamation for Software Updates in Virtual Machine Environments.
Proceedings of the International Conference on Networking, Architecture, and Storage, 2009

Using Pcache to Speedup Interpretation in Dynamic Binary Translation.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2009

On the capacity of bounded rank modulation for flash memories.
Proceedings of the IEEE International Symposium on Information Theory, 2009

A Light-weight Code Cache Design for Dynamic Binary Translation.
Proceedings of the 15th IEEE International Conference on Parallel and Distributed Systems, 2009

An accurate and efficient performance analysis approach based on queuing model for network on chip.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Fast, On-Demand Software Deployment with Lightweight, Independent Virtual Disk Images.
Proceedings of the Eighth International Conference on Grid and Cooperative Computing, 2009

Integration of the dynamic, mutual evaluating and role-based iterated revision belief into collaborative conceptual modeling.
Proceedings of the 2009 International Symposium on Collaborative Technologies and Systems, 2009

Dynamically utilizing computation accelerators for extensible processors in a software approach.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

A Hardware Approach for Reducing Interpretation Overhead.
Proceedings of the Ninth IEEE International Conference on Computer and Information Technology, 2009

2008
A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique.
J. Electronic Testing, 2008

Research of a Secure File System for Protection of Intellectual Property Right.
Proceedings of the Ninth International Conference on Web-Age Information Management, 2008

Control flow checking and recovering based on 8051 architecture.
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

Hierarchical memory system design for a heterogeneous multi-core processor.
Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), 2008

Transient Fault Tolerance on Chip Multiprocessor Based on Dual and Triple Core Redundancy.
Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008

A New CORDIC Algorithm and Software Implementation Based on Synchronized Data Triggering Architecture.
Proceedings of the 2008 International Conference on Multimedia and Ubiquitous Engineering (MUE 2008), 2008

Performance Bound Analysis and Retiming of Timed Circuits.
Proceedings of the 9th International Conference for Young Computer Scientists, 2008

The P2P Communication Model for a Local Memory based Multi-core Processor.
Proceedings of the 9th International Conference for Young Computer Scientists, 2008

Transient Fault Recovery on Chip Multiprocessor based on Dual Core Redundancy and Context Saving.
Proceedings of the 9th International Conference for Young Computer Scientists, 2008

Low-Level Component for OpenGL ES Oriented Heterogeneous Architecture with Optimization.
Proceedings of the 9th International Conference for Young Computer Scientists, 2008

A Novel Hardware Assisted Full Virtualization Technique.
Proceedings of the 9th International Conference for Young Computer Scientists, 2008

An Optimized COW Block Device Driver in VMM for Fast, On-Demand Software Deployment.
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008

DBTIM: An Advanced Hardware Assisted Full Virtualization Architecture.
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008

A Framework to Evaluate the Trade-off among AVF Performance and Area of Soft Error Tolerant Microprocessors.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques.
Proceedings of the 45th Design Automation Conference, 2008

A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers.
Proceedings of the 45th Design Automation Conference, 2008

Using an Automated Approach to Explore and Design a High-Efficiency Processor Element for the Multimedia Domain.
Proceedings of the Second International Conference on Complex, 2008

Escaping from Blocking: A Dynamic Virtual Channel for Pipelined Routers.
Proceedings of the Second International Conference on Complex, 2008

Memory System Design for a Multi-core Processor.
Proceedings of the Second International Conference on Complex, 2008

2007
Design and Test of Self-checking Asynchronous Control Circuit.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Template Vertical Dictionary-Based Program Compression Scheme on the TTA.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

The Research of an Embedded Processor Element for Multimedia Domain.
Proceedings of the Multimedia Content Analysis and Mining, International Workshop, 2007

Instruction Selection for Subword Level Parallelism Optimizations for Application Specific Instruction Processors.
Proceedings of the Parallel and Distributed Processing and Applications, 2007

Security Event Management System based on Mobile Agent Technology.
Proceedings of the IEEE International Conference on Intelligence and Security Informatics, 2007

Study on Key Technologies of Shipbuilding Virtual Enterprise Information Integration Oriented Agile Manufacturing.
Proceedings of the Research and Practical Issues of Enterprise Information Systems II, 2007

A Distributed Cut Set Discovery Algorithm in P2P Environment.
Proceedings of the 2007 International Conference on Parallel Processing Workshops (ICPP Workshops 2007), 2007

Latency Estimation of the Asynchronous Pipeline Using the Max-Plus Algebra.
Proceedings of the Computational Science - ICCS 2007, 7th International Conference, Beijing, China, May 27, 2007

An Interest-Based Intelligent Link Selection Algorithm in Unstructured P2P Environment.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2007

A Low-Power Globally Synchronous Locally Asynchronous FFT Processor.
Proceedings of the High Performance Computing and Communications, 2007

A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design.
Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 2007

An Optimal Design Method for De-synchronous Circuit Based on Control Graph.
Proceedings of the Advanced Parallel Processing Technologies, 7th International Symposium, 2007

Design of a Low-Power Embedded Processor Architecture Using Asynchronous Function Units.
Proceedings of the Advances in Computer Systems Architecture, 2007

A Low-Power Application Specific Instruction Set Processor Using Asynchronous Function Units.
Proceedings of the Seventh International Conference on Computer and Information Technology (CIT 2007), 2007

2006
Research and Implementation of a 32-Bit Asynchronous Multiplier.
Journal of Computer Research and Development, 2006

Robust AM-MIMO based on minimized transmission power.
IEEE Communications Letters, 2006

Secure Data Transmission on Multiple Paths in Mobile Ad Hoc Networks.
Proceedings of the Wireless Algorithms, 2006

A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology.
Proceedings of the IFIP VLSI-SoC 2006, 2006

An Efficient Way to Build Secure Disk.
Proceedings of the Information Security Practice and Experience, 2006

A PCA-LVQ Model for Intrusion Alert Analysis.
Proceedings of the Intelligence and Security Informatics, 2006

A minimum transmission power AM-MIMO system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Intrusion Alert Analysis Based on PCA and the LVQ Neural Network.
Proceedings of the Neural Information Processing, 13th International Conference, 2006

A Novel Data-Parallel Coprocessor for Multimedia Signal Processing.
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006

A Heterogeneous Embedded MPSoC for Multimedia Applications.
Proceedings of the High Performance Computing and Communications, 2006

A High Performance Heterogeneous Architecture and Its Optimization Design.
Proceedings of the High Performance Computing and Communications, 2006

A Hyper-cube based P2P Information Service for Data Grid.
Proceedings of the Grid and Cooperative Computing, 2006

Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Power Optimization of Interconnection Networks for Transport Triggered Architecture.
Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006

A Dual-core Embedded System-on-Chip Architecture for Multimedia Signal Processing Applications.
Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006

Improving the Fault Tolerance of a Computer System with Space-Time Triple Modular Redundancy.
Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006

Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor Using WDDL and Wave-Pipelining.
Proceedings of the Information Security and Cryptology, Second SKLOIS Conference, 2006

A Dynamic Trust Model Based on Feedback Control Mechanism for P2P Applications.
Proceedings of the Autonomic and Trusted Computing, Third International Conference, 2006

Cycle Period Analysis and Optimization of Timed Circuits.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

A Heterogeneous Multi-core Processor Architecture for High Performance Computing.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

An Approximate Method for Performance Evaluation of Asynchronous Pipeline Rings.
Proceedings of the Sixth International Conference on Computer and Information Technology (CIT 2006), 2006

Two New Space-Time Triple Modular Redundancy Techniques for Improving Fault Tolerance of Computer Systems.
Proceedings of the Sixth International Conference on Computer and Information Technology (CIT 2006), 2006

2005
A Channel Estimation Scheme for MIMO-MC-CDMA Downlink in High Mobility Environments.
IEICE Transactions, 2005

Design and Implementation a TPM Chip SUP320 by SOC.
Proceedings of the Security and Privacy in the Age of Ubiquitous Computing, IFIP TC11 20th International Conference on Information Security (SEC 2005), May 30, 2005

Research on Risk Probability Estimating Using Fuzzy Clustering for Dynamic Security Assessment.
Proceedings of the Rough Sets, 2005

Trust-Enhanced Alteration Scenario for Universal Computer.
Proceedings of the 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 2005

Protecting Mass Data Basing on Small Trusted Agent.
Proceedings of the Information Security Practice and Experience, 2005

Design of a Configurable Embedded Processor Architecture for DSP Functions.
Proceedings of the 11th International Conference on Parallel and Distributed Systems, 2005

Research on Fuzzy Group Decision Making in Security Risk Assessment.
Proceedings of the Networking, 2005

An Optimal Component Distribution Algorithm Based on MINLP.
Proceedings of the Networking and Mobile Computing, Third International Conference, 2005

A Fast Motion Estimation Algorithm Based on Diamond and Triangle Search Patterns.
Proceedings of the Pattern Recognition and Image Analysis, Second Iberian Conference, 2005

Transmit power and bit allocation for the MIMO system.
Proceedings of the Global Telecommunications Conference, 2005. GLOBECOM '05, St. Louis, Missouri, USA, 28 November, 2005

Retargetable Machine-Description System: Multi-layer Architecture Approach.
Proceedings of the Grid and Cooperative Computing - GCC 2005, 4th International Conference, Beijing, China, November 30, 2005

Research on intra modes for inter-frame coding in H.264.
Proceedings of the Ninth International Conference on Computer Supported Cooperative Work in Design, 2005

A Fast Motion Estimation Algorithm Based on Diamond and Simplified Square Search Patterns.
Proceedings of the Progress in Pattern Recognition, 2005

Implementing Component Persistence in CCM Based on StarPSS.
Proceedings of the Advanced Parallel Processing Technologies, 6th InternationalWorkshop, 2005

Research on Fast Block Participation Mode Selection Algorithm in H.264.
Proceedings of the 4th Annual ACIS International Conference on Computer and Information Science (ICIS 2005), 2005

2004
Protect Data Stored on Remote Server.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004

Building Efficient and Secure Communication for Grid.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004

A Case of SCMP with TLS.
Proceedings of the Parallel and Distributed Processing and Applications, 2004

Protecting integrity and confidentiality for data communication.
Proceedings of the 9th IEEE Symposium on Computers and Communications (ISCC 2006), June 28, 2004

A New Technique for Program Code Compression in Embedded Microprocessor.
Proceedings of the Embedded Software and Systems, First International Conference, 2004

Modeling Time-Related Trust.
Proceedings of the Grid and Cooperative Computing, 2004

Verify Memory Integrity Basing on Hash Tree and MAC Combined Approach.
Proceedings of the Embedded and Ubiquitous Computing, 2004

Analysis of Inter-Frame Coding Without Intra Modes in H.264.
Proceedings of the 7th Eurographics Multimedia Workshop 2004, 2004

Improving Security Architecture Development Based on Multiple Criteria Decision Making.
Proceedings of the Content Computing, Advanced Workshop on Content Computing, 2004

TengYue-1TengYue: In Chinese means jump over.: A High Performance Embedded SoC.
Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004

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Avoid Powerful Tampering by Malicious Host.
Proceedings of the Grid and Cooperative Computing, Second International Workshop, 2003

Predicate Analysis Based on Path Information.
Proceedings of the Advanced Parallel Programming Technologies, 5th International Workshop, 2003

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A new integrated system of logic programming and relational database.
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Design and evaluation of a relational knowledge base prototype machine.
Future Generation Comp. Syst., 1990


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