Sachhidh Kannan

According to our database, Sachhidh Kannan authored at least 11 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

SCANN: Side Channel Analysis of Spiking Neural Networks.

Karthikeyan Nagarajan, Rupshali Roy, Rasit Onur Topaloglu, Sachhidh Kannan, Swaroop Ghosh

Cryptogr., June, 2023

2022

Analysis of Power-Oriented Fault Injection Attacks on Spiking Neural Networks.

Karthikeyan Nagarajan, Junde Li, Sina Sayyah Ensan, Mohammad Nasim Imtiaz Khan, Sachhidh Kannan, Swaroop Ghosh

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2015

Security Vulnerabilities of Emerging Nonvolatile Main Memories and Countermeasures.

Sachhidh Kannan, Naghmeh Karimi, Ozgur Sinanoglu, Ramesh Karri

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories.

Sachhidh Kannan, Naghmeh Karimi, Ramesh Karri, Ozgur Sinanoglu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014

Detection, diagnosis, and repair of faults in memristor-based memories.

Sachhidh Kannan, Naghmeh Karimi, Ramesh Karri, Ozgur Sinanoglu

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Secure Memristor-based Main Memory.

Sachhidh Kannan, Naghmeh Karimi, Ozgur Sinanoglu

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Sneak-path Testing of Memristor-based Memories.

Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Sneak path testing and fault modeling for multilevel memristor-based memories.

Sachhidh Kannan, Ramesh Karri, Ozgur Sinanoglu

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012

Engineering crossbar based emerging memory technologies.

Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011

3D NOC for many-core processors.

Aamir Zia, Sachhidh Kannan, H. Jonathan Chao, Garrett S. Rose

Microelectron. J., 2011

A hierarchical 3-D floorplanning algorithm for many-core CMP networks.

Sachhidh Kannan, Garrett S. Rose

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011