Abhijit Ghosh

Orcid: 0000-0002-0557-2839

According to our database1, Abhijit Ghosh authored at least 33 papers between 1989 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Neural Shading Fields for Efficient Facial Inverse Rendering.
Comput. Graph. Forum, October, 2023

2022
High-performance computation of pricing two-asset American options under the Merton jump-diffusion model on a GPU.
Comput. Math. Appl., 2022

2021
A Parallel Cyclic Reduction Algorithm for Pentadiagonal Systems with Application to a Convection-Dominated Heston PDE.
SIAM J. Sci. Comput., 2021

Highly efficient parallel algorithms for solving the Bates PIDE for pricing options on a GPU.
Appl. Math. Comput., 2021

2017
Regularized Stacked Auto-Encoder Based Pre-training for Generalization of Multi-layer Perceptron.
Proceedings of the Theory and Practice of Natural Computing - 6th International Conference, 2017

2000
Formal Verification of Synthesized Mixed Signal Designs Using *BMDs.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

YAML: A Tool for Hardware Design Visualization and Capture.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Methodology for hardware/software co-verification in C/C++ (short paper).
Proceedings of ASP-DAC 2000, 2000

1999
Formal Verification of Synthesized Analog Designs.
Proceedings of the IEEE International Conference On Computer Design, 1999

Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Hardware Synthesis from C/C++.
Proceedings of the 1999 Design, 1999

1998
A Methodology for Feature Interaction Detection in the AIN 0.1 Framework.
IEEE Trans. Software Eng., 1998

Sequential logic optimization for low power using input-disabling precomputation architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997
Estimation of average switching activity in combinational logic circuits using symbolic simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1996
An observability-based code coverage metric for functional simulation.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995
Probabilistic manipulation of Boolean functions using free Boolean diagrams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Optimization of combinational and sequential logic circuits for low power using precomputation.
Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994
Precomputation-based sequential logic optimization for low power.
IEEE Trans. Very Large Scale Integr. Syst., 1994

1993
Sequential test generation and synthesis for testability at the register-transfer and logic levels.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Probabilistic construction and manipulation of free Boolean diagrams.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Retiming sequential circuits for low power.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Boolean factorization using multiple-valued minimization.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
Heuristic minimization of Boolean relations using testing techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Boolean satisfiability and equivalence checking using general Binary Decision Diagrams.
Integr., 1992

On average power dissipation and random pattern testability of CMOS combinational logic networks.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Estimation of Average Switching Activity in Combinational and Sequential Circuits.
Proceedings of the 29th Design Automation Conference, 1992

1991
Test generation and verification for highly sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Recent progress in synthesis for testability.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

1990
Sequential logic synthesis for testability using register-transfer level descriptions.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Sequential Test Generation at the Register-Transfer and Logic Levels.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Verification of Interacting Sequential Circuits.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
Test generation for highly sequential circuits.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989


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