A. Richard Newton

Affiliations:
  • University of California, Berkeley, USA


According to our database1, A. Richard Newton authored at least 104 papers between 1980 and 2006.

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Bibliography

2006
Fast Boolean Matching with Don't Cares.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005
Recognition and beautification of multi-stroke symbols in digital ink.
Comput. Graph., 2005

2004
Robust sketched symbol fragmentation using templates.
Proceedings of the 9th International Conference on Intelligent User Interfaces, 2004

Digital Image Restoration by Exposure-Splitting and Registration.
Proceedings of the 17th International Conference on Pattern Recognition, 2004

Sketched Symbol Recognition using Zernike Moments.
Proceedings of the 17th International Conference on Pattern Recognition, 2004

Great works for the 21st century: a critical role for the modern research university.
Proceedings of the EMSOFT 2004, 2004

2002
From ASIC to ASIP: The Next Design Discontinuity.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001
Learning as applied to stochastic optimization for standard-cellplacement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Limitations and challenges of computer-aided design technology for CMOS VLSI.
Proc. IEEE, 2001

2000
System-level design: orthogonalization of concerns andplatform-based design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Integration of retiming with architectural floorplanning.
Integr., 2000

Embedded systems design in the new millennium (panel session).
Proceedings of the 37th Conference on Design Automation, 2000

Predicting performance potential of modern DSPs.
Proceedings of the 37th Conference on Design Automation, 2000

Retargetable estimation scheme for DSP architecture selection.
Proceedings of ASP-DAC 2000, 2000

1999
The MARCO/DARPA Gigascale Silicon Research Center.
Proceedings of the IEEE International Conference On Computer Design, 1999

Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Learning as applied to stochastic optimization for standard cell placement.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Design and Specification of Embedded Systems in Java Using Successive, Formal Refinement.
Proceedings of the 35th Conference on Design Automation, 1998

Technical Challenges of IP and System-on-Chip: The ASIC Vendor Perspective (Panel).
Proceedings of the 35th Conference on Design Automation, 1998

WELD - An Environment for Web-based Electronic Design.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Formal methods into practice: case studies in the application of the B method.
IEE Proc. Softw. Eng., 1997

The future of logic synthesis and physical design in deep-submicron process geometries.
Proceedings of the 1997 International Symposium on Physical Design, 1997

Engineering change for power optimization using global sensitivity and synthesis flexibility.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

EDA and the network.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Adaptive methods for netlist partitioning.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Logic synthesis for large pass transistor circuits.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996
On estimation accuracy for guiding low-power resynthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Logic synthesis using power-sensitive don't care sets.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

The maximal VHDL subset with a cycle-level abstraction.
Proceedings of the conference on European design automation, 1996

1995
An estimation technique to guide low power resynthesis algorithms.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

1994
Algorithms for the transient simulation of lossy interconnect.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

TOBAC: A Test Case Browser for Testing Object-Oriented Software.
Proceedings of the 1994 International Symposium on Software Testing and Analysis, 1994

Mixed-mode simulation and analog multilevel simulation.
The Kluwer international series in engineering and computer science, Kluwer, ISBN: 978-0-7923-9473-0, 1994

1993
Sequential test generation and synthesis for testability at the register-transfer and logic levels.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Two-Level Minimization of Multivalued Functions with Large Offsets.
IEEE Trans. Computers, 1993

1992
Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Heuristic minimization of Boolean relations using testing techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

An exact analytic technique for simulating uniform RC lines.
Proceedings of the conference on European design automation, 1992

Experiments on the synthesis and testability of non-scan finite state machines.
Proceedings of the conference on European design automation, 1992

Simulating Lossy Interconnect with High Frequency Nonidealities in Linear Time.
Proceedings of the 29th Design Automation Conference, 1992

1991
Reduced offsets for minimization of binary-valued functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

An efficient verifier for finite state machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Test generation and verification for highly sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

MUSE: a multilevel symbolic encoding algorithm for state assignment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Exact algorithms for output encoding, state assignment, and four-level Boolean minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Irredundant interacting sequential machines via optimal logic synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Optimum and heuristic algorithms for an approach to finite state machine decomposition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Has CAD for VLSI Reached a Dead End?
Proceedings of the VLSI 91, 1991

Exact Redundant State Registers Removal Based on Binary Decision Diagrams.
Proceedings of the VLSI 91, 1991

Implicit Manipulation of Equivalence Classes Using Binary Decision Diagrams.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

An Impulse-Response Based Linear Time-Complexity Algorithm for Lossy Interconnect Simulation.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A Cell-Replicating Approach to Minicut-Based Circuit Partitioning.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Framework Standards: How Important are They? (Panel Abstract).
Proceedings of the 28th Design Automation Conference, 1991

1990
A circuit disassembly technique for synthesizing symbolic layouts from mask descriptions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Irredundant sequential machines via optimal logic synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Redundancies and don't cares in sequential logic synthesis.
J. Electron. Test., 1990

Sequential logic synthesis for testability using register-transfer level descriptions.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

An Empirical Evaluation of Two Memory-Efficient Directory Methods.
Proceedings of the 17th Annual International Symposium on Computer Architecture, 1990

Testability driven synthesis of interacting finite state machines.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

Don't Care Minimization of Multi-Level Sequential Logic Networks.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and Test.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Abstract Data Types and High-Level Synthesis.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Standards, Openness and Design Environments in Electronic Design Automation (Panel Abstract).
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Reduced Offsets for Two-Level Multi-Valued Logic Minimization.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Sequential Test Generation at the Register-Transfer and Logic Levels.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Verification of Interacting Sequential Circuits.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Design Management Based on Design Traces.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Electrical-logic simulation and its applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Decomposition and factorization of sequential finite state machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Algorithms for hardware allocation in data path synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

A synthesis and optimization procedure for fully and easily testable sequential machines.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

A generalized approach to the constrained cubical embedding problem.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989

Test generation for highly sequential circuits.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

SLIP: a software environment for system level interactive partitioning.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Optimum and heuristic algorithms for finite state machine decomposition and partitioning.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Easily testable PLA-based finite state machines.
Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

Protection and Versioning for OCT.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988
Test generation for sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

MUSTANG: state assignment of finite state machines targeting multilevel logic implementations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

On the verification of sequential machines at differing levels of abstraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

An Incomplete Scan Design Approach to Test Generation for Sequential Machines.
Proceedings of the Proceedings International Test Conference 1988, 1988

Synthesis and Optimization Procedures for Fully and Easily Testable Sequential Machines.
Proceedings of the Proceedings International Test Conference 1988, 1988

Critic: a knowledge-based program for critiquing circuit designs.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

A modified approach to two-level logic minimization.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Boolean decomposition in multi-level logic optimization.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Twenty-Five Years of Electronic Design Automation.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
Topological Optimization of Multiple-Level Array Logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

KAHLUA: A Hierarchical Circuit Disassembler.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986
Computer-Aided Design for VLSI Circuits.
Computer, 1986

Highlights of VLSI Research at Berkeley.
Proceedings of the Fall Joint Computer Conference, November 2-6, 1986, Dallas, Texas, USA, 1986

An empirical analysis of the performance of a multiprocessor-based circuit simulator.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

An accuration delay modeling technique for switch-level timing verification.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

GENIE: a generalized array optimizer for VLSI synthesis.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985
Design Aids for VLSI: A Perspective Revisited.
IEEE Des. Test, 1985

1984
Relaxation-Based Electrical Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

A multiprocessor implementation of relaxation-based electrical circuit simulation.
Proceedings of the 21st Design Automation Conference, 1984

1983
Symmetric Displacement Algorithms for the Timing Analysis of Large Scale Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

1982
An Algorithm for Optimal PLA Folding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1982

A symbolic design system for integrated circuits.
Proceedings of the 19th Design Automation Conference, 1982

Techniques for programmable logic array folding.
Proceedings of the 19th Design Automation Conference, 1982

KIC2: A Low-Cost, Interactive Editor for Integrated Circuit Design.
Proceedings of the COMPCON'82, 1982

1980
The VLSI design challenge of the 80's (Position Statement).
Proceedings of the 17th Design Automation Conference, 1980


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