Marios C. Papaefthymiou

According to our database1, Marios C. Papaefthymiou authored at least 89 papers between 1991 and 2018.

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Bibliography

2018
Rethinking Numerical Representations for Deep Neural Networks.
CoRR, 2018

A 0.23mW Heterogeneous Deep-Learning Processor Supporting Dynamic Execution of Conditional Neural Networks.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017
20.7 A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 1.25pJ/bit 0.048mm<sup>2</sup> AES core with DPA resistance for IoT devices.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A 5.5GHz 0.84TOPS/mm<sup>2</sup> neural network engine with stream architecture and resonant clock mesh.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
1.32GHz high-throughput charge-recovery AES core with resistance to DPA attacks.
Proceedings of the Symposium on VLSI Circuits, 2015

A 934MHz 9Gb/s 3.2pJ/b/iteration charge-recovery LDPC decoder with in-package inductors.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
27.6 An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
Designing for Responsiveness with Computational Sprinting.
IEEE Micro, 2013

Utilizing Dark Silicon to Save Energy with Computational Sprinting.
IEEE Micro, 2013

Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor.
IEEE J. Solid State Circuits, 2013

Computational sprinting on a hardware/software testbed.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2013

2012
Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Computational sprinting.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011
A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
187 MHz Subthreshold-Supply Charge-Recovery FIR.
IEEE J. Solid State Circuits, 2010

2009
A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

A resonant-clock 200MHz ARM926EJ-STM microcontroller.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
Resonant-Clock Latch-Based Design.
IEEE J. Solid State Circuits, 2008

2007
A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Energy-Efficient GHz-Class Charge-Recovery Logic.
IEEE J. Solid State Circuits, 2007

Skew spreading for peak current reduction.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Practical repeater insertion for low power: what repeater library do we need?
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Parallelizing post-placement timing optimization.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
HyPE: hybrid power estimation for IP-based systems-on-chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Charge-Recovery Computing on Silicon.
IEEE Trans. Computers, 2005

Multi-Session Partitioning for Parallel Timing Optimization.
Proceedings of the Sixth International Conference on Parallel and Distributed Computing, 2005

Boost Logic: A High Speed Energy Recovery Circuit Family.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Two-Phase Resonant Clock Distribution.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A GHz-class charge recovery logic.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power.
Proceedings of the 2005 Design, 2005

Fast, efficient, recovering, and irreversible.
Proceedings of the Second Conference on Computing Frontiers, 2005

2004
A Markov chain sequence generator for power macromodeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Clock tree layout design for reduced delay uncertainty.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

A synchronous interface for SoCs with multiple clock domains.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Experimental Evaluation of Resonant Clock Distribution.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Constant-load energy recovery memory for efficient high-speed operation.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Empirical evaluation of timing and power in resonant clock distribution.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An Algorithm for Geometric Load Balancing with Two Constraints.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2003
Design of a 20-mb/s 256-state Viterbi decoder.
IEEE Trans. Very Large Scale Integr. Syst., 2003

A true single-phase energy-recovery multiplier.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Block-based multiperiod dynamic memory design for low data-retention power.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Fine-grain real-time reconfigurable pipelining.
IBM J. Res. Dev., 2003

Energy Recovering ASIC Design.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

A 225 MHz resonant clocked ASIC chip.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Reduced Delay Uncertainty in High Performance Clock Distribution Networks.
Proceedings of the 2003 Design, 2003

HyPE: hybrid power estimation for IP-based programmable systems.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Retiming and clock scheduling for digital circuit optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Energy recovering static memory.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Incorporation of input glitches into power macromodeling.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Design of a high-throughput low-power IS95 Viterbi decoder.
Proceedings of the 39th Design Automation Conference, 2002

2001
True single-phase adiabatic circuitry.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Symbolic debugging of embedded hardware and software.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

A resonant clock generator for single-phase adiabatic systems.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A static power estimation methodolodgy for IP-based design.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

A True Single-Phase 8-bit Adiabatic Multiplier.
Proceedings of the 38th Design Automation Conference, 2001

Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier.
Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001

2000
Optimizing computations for effective block-processing.
ACM Trans. Design Autom. Electr. Syst., 2000

Dynamic Memory Design for Low Data-Retention Power.
Proceedings of the Integrated Circuit Design, 2000

Symbolic debugging of globally optimized behavioral specifications.
Proceedings of ASP-DAC 2000, 2000

1999
Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors.
Des. Autom. Embed. Syst., 1999

Single-phase source-coupled adiabatic logic.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Analytical macromodeling for high-level power estimation.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits.
Proceedings of the 1999 Design, 1999

Maximizing Performance by Retiming and Clock Skew Scheduling.
Proceedings of the 36th Conference on Design Automation, 1999

1998
True single-phase energy-recovering logic for low-power, high-speed VLSI.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Asymptotically efficient retiming under setup and hold constraints.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997
Retiming edge-triggered circuits under general delay models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Optimizing two-phase, level-clocked circuitry.
J. ACM, 1997

Computing Strictly-Second Shortest Paths.
Inf. Process. Lett., 1997

Performance Evaluation of Gang Scheduling for Parallel and Distributed Multiprogramming.
Proceedings of the Job Scheduling Strategies for Parallel Processing, 1997

1996
Stochastic Analysis of Gang Scheduling in Parallel and Distributed Systems.
Perform. Evaluation, 1996

An Analysis of Gang Scheduling for Multiprogrammed Parallel Computing Environments.
Proceedings of the 8th Annual ACM Symposium on Parallel Algorithms and Architectures, 1996

A Gang Scheduling Design for Multiprogrammed Parallel Computing Environments.
Proceedings of the Job Scheduling Strategies for Parallel Processing, 1996

Fixed-phase retiming for low power design.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Optimizing Systems for Effective Block-Processing: The <i>k</i>-Delay Problem.
Proceedings of the 33st Conference on Design Automation, 1996

1995
DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling.
Proceedings of the 32st Conference on Design Automation, 1995

Efficient retiming under a general delay model.
Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994
Precomputation-based sequential logic optimization for low power.
IEEE Trans. Very Large Scale Integr. Syst., 1994

Understanding Retiming Through Maximum Avarage-Delay Cycles.
Math. Syst. Theory, 1994

Memory Assignment for Multiprocessor Caches through Grey Coloring.
Proceedings of the PARLE '94: Parallel Architectures and Languages Europe, 1994

Implementing parallel shortest-paths algorithms.
Proceedings of the Parallel Algorithms, 1994

1993
TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1991
Understanding Retiming Through Maximum Average-Weight Cycles.
Proceedings of the 3rd Annual ACM Symposium on Parallel Algorithms and Architectures, 1991


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