Alessandro Nadalini

Orcid: 0009-0007-3574-7576

According to our database1, Alessandro Nadalini authored at least 8 papers between 2022 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Temporal Lockstep: Low-Cost Resilient Design for Microcontroller-Class RISC-V Processors.
IEEE Access, 2026

2025
FlatAttention: Dataflow and Fabric Collectives Co-Optimization for Efficient Multi-Head Attention on Tile-Based Many-PE Accelerators.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025

FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators.
Proceedings of the 22nd ACM International Conference on Computing Frontiers, 2025

2024
A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024

2023
DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training.
CoRR, 2023

A 3 TOPS/W RISC-V Parallel Cluster for Inference of Fine-Grain Mixed-Precision Quantized Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023


2022
Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022


  Loading...