Alexandru Andrei

According to our database1, Alexandru Andrei authored at least 28 papers between 2004 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2017
A Neural Probe With Up to 966 Electrodes and Up to 384 Configurable Channels in 0.13 µm SOI CMOS.
IEEE Trans. Biomed. Circuits Syst., 2017

Time Multiplexed Active Neural Probe with 1356 Parallel Recording Sites.
Sensors, 2017

Latency-Aware Packet Processing on CPU-GPU Heterogeneous Systems.
Proceedings of the 54th Annual Design Automation Conference, 2017

Ultra-thin biocompatible implantable chip for bidirectional communication with peripheral nerves.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
22.7 A 966-electrode neural probe with 384 configurable channels in 0.13µm SOI CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Time multiplexed active neural probe with 678 parallel recording sites.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2014
An Implantable 455-Active-Electrode 52-Channel CMOS Neural Probe.
IEEE J. Solid State Circuits, 2014

2012
Temperature-Aware Idle Time Distribution for Leakage Energy Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Fabrication and successful in-vivo implantation of a flexible neural implant with a hybrid polyimide-silicon design.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

2011
Quasi-Static Voltage Scaling for Energy Minimization With Time Constraints.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Effect of Insertion Speed on Tissue Response and Insertion Mechanics of a Chronically Implanted Silicon-Based Neural Probe.
IEEE Trans. Biomed. Eng., 2011

Chronic behavior evaluation of a micro-machined neural implant with optimized design based on an experimentally derived model.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Predictable Worst-Case Execution Time Analysis for Multiprocessor Systems-on-Chip.
Proceedings of the Sixth IEEE International Symposium on Electronic Design, 2011

On-line Temperature-Aware Idle Time Distribution for Leakage Energy Optimization.
Proceedings of the Sixth IEEE International Symposium on Electronic Design, 2011

2010
Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration.
Proceedings of the 46th Design Automation Conference, 2009

2008
Timing analysis of the FlexRay communication protocol.
Real Time Syst., 2008

Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage Scaling.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Temperature-Aware Voltage Selection for Energy Optimization.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Energy Efficient and Predictable Design of Real-Time Embedded Systems.
PhD thesis, 2007

Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip.
Proceedings of the 28th IEEE Real-Time Systems Symposium (RTSS 2007), 2007

2006
A Cooperative, Accurate Solving Framework for Optimal Allocation, Scheduling and Frequency Selection on Energy-Efficient MPSoCs.
Proceedings of the International Symposium on System-on-Chip, 2006

2005
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints.
Proceedings of the 2005 Design, 2005

2004
Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems.
Proceedings of the 2004 Design, 2004


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