An Chen

Affiliations:
  • IBM Research - Almaden, San Jose, CA, USA


According to our database1, An Chen authored at least 14 papers between 2019 and 2025.

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Bibliography

2025
Rapid yet accurate Tile-circuit and device modeling for Analog In-Memory Computing.
CoRR, June, 2025

Analog Foundation Models.
CoRR, May, 2025

2023
An analog-AI chip for energy-efficient speech recognition and transcription.
Nat., 2023

Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators.
CoRR, 2023

Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited).
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited).
Proceedings of the IEEE International Reliability Physics Symposium, 2023

2022
Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices.
Frontiers Comput. Neurosci., 2021

Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Optimization of Analog Accelerators for Deep Neural Networks Inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Neuromorphic Computing with Phase Change, Device Reliability, and Variability Challenges.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Accelerating Deep Neural Networks with Analog Memory Devices.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019
AI hardware acceleration with analog memory: Microarchitectures for low energy at high speed.
IBM J. Res. Dev., 2019


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