Manuel Le Gallo
Orcid: 0000-0003-1600-6151
According to our database1,
Manuel Le Gallo authored at least 69 papers
between 2015 and 2026.
Collaborative distances:
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Bibliography
2026
A 1.92um Pitch Current-Controlled Oscillator ADC Array Featuring Charge-Injection-Based Two-Stage Conversion for In-Memory Computing.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
2025
Efficient scaling of large language models with mixture of experts and 3D analog in-memory computing.
Nat. Comput. Sci., January, 2025
Nat. Mac. Intell., 2025
A framework for analog-digital mixed-precision neural network training and inference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
Analog AI Accelerators for Transformer-based Language Models: Hardware, Workload, and Power Performance.
Proceedings of the IEEE International Memory Workshop, 2025
Analog-AI Hardware Accelerators for Low-Latency Transformer-Based Language Models (Invited).
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
Designing Circuits for AiMC Based on Non-Volatile Memories: A Tutorial Brief on Trade-Off and Strategies for ADCs and DACs Co-Design.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
CoRR, 2024
Improving the Accuracy of Analog-Based In-Memory Computing Accelerators Post-Training.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
A Precision-Optimized Fixed-Point Near-Memory Digital Processing Unit for Analog In-Memory Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2023
Programming Weights to Analog In-Memory Computing Cores by Direct Minimization of the Matrix-Vector Multiplication Error.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023
Using the IBM Analog In-Memory Hardware Acceleration Kit for Neural Network Training and Inference.
CoRR, 2023
Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators.
CoRR, 2023
AnalogNAS: A Neural Network Design Framework for Accurate Inference with Analog In-Memory Computing.
Proceedings of the IEEE International Conference on Edge Computing and Communications, 2023
2022
Precision of bit slicing with in-memory computing based on analog phase-change memory crossbars.
Neuromorph. Comput. Eng., 2022
Neuromorph. Comput. Eng., 2022
ML-HW Co-Design of Noise-Robust TinyML Models and Always-On Analog Compute-in-Memory Edge Accelerator.
IEEE Micro, 2022
HERMES-Core - A 1.59-TOPS/mm<sup>2</sup> PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs.
IEEE J. Solid State Circuits, 2022
MNEMOSENE: Tile Architecture and Simulator for Memristor-based Computation-in-memory.
ACM J. Emerg. Technol. Comput. Syst., 2022
A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference.
CoRR, 2022
In-memory Realization of In-situ Few-shot Continual Learning with a Dynamically Evolving Explicit Memory.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
2021
A Multi-Memristive Unit-Cell Array With Diagonal Interconnects for In-Memory Computing.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Energy Efficient In-Memory Hyperdimensional Encoding for Spatio-Temporal Signal Processing.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Nat., 2021
ERCIM News, 2021
AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory Accelerator.
CoRR, 2021
Measurement of onset of structural relaxation in melt-quenched phase change materials.
CoRR, 2021
HERMES Core - A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
A Flexible and Fast PyTorch Toolkit for Simulating Training and Inference on Analog Crossbar Arrays.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
Real-time Language Recognition using Hyperdimensional Computing on Phase-change Memory Array.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
ESSOP: Efficient and Scalable Stochastic Outer Product Architecture for Deep Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
CoRR, 2019
CoRR, 2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the Device Research Conference, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
ERCIM News, 2018
Proceedings of the Non-Volatile Memory Technology Symposium, 2018
Mixed-precision architecture based on computational memory for training deep neural networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
CoRR, 2017
Proceedings of the 17th Non-Volatile Memory Technology Symposium, 2017
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
2016
Proceedings of the 46th European Solid-State Device Research Conference, 2016
2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015