Andy Dewilde

According to our database1, Andy Dewilde authored at least 9 papers between 2004 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
A 100 Gbps LDPC Decoder for the IEEE 802.11ay Standard.
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

2017
A 79-GHz 2 × 2 MIMO PMCW Radar SoC in 28-nm CMOS.
IEEE J. Solid State Circuits, 2017

2016
A 79GHz 2×2 MIMO PMCW radar SoC in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Parallelized correlator bank for a 1 GHz bandwidth phase modulated CW radar in the 79GHz band.
Proceedings of the 2015 IEEE Symposium on Communications and Vehicular Technology in the Benelux, 2015

An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2012
DART - a High Level Software-Defined Radio Platform Model for Developing the Run-Time Controller.
J. Signal Process. Syst., 2012

A flexible platform architecture for Gbps wireless communication.
Proceedings of the 2012 International Symposium on System on Chip, 2012

2004
Real Time Prototyping of Broadband Wireless LAN Systems.
Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 2004

A Power Optimized Display Memory Organization for Handheld User Terminal.
Proceedings of the 2004 Design, 2004


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