Meng Li

Orcid: 0000-0002-8067-3285

Affiliations:
  • IMEC, Perceptive Systems Department, Leuven, Belgium
  • Telecom Bretagne, Brest, France (PhD 2012)


According to our database1, Meng Li authored at least 16 papers between 2009 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2021
High-Speed LDPC Decoders Towards 1 Tb/s.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2018
A 100 Gbps LDPC Decoder for the IEEE 802.11ay Standard.
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

2016
Computation-skip Error Mitigation Scheme for Power Supply Voltage Scaling in Recursive Applications.
J. Signal Process. Syst., 2016

An Energy-Efficient Reconfigurable ASIP Supporting Multi-mode MIMO Detection.
J. Signal Process. Syst., 2016

An Information Theory Perspective for the Binary STT-MRAM Cell Operation Channel.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

2015
Max-log demapper architecture design for DVB-T2 rotated QAM constellations.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
Computation-skip error resilient scheme for recursive CORDIC.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Towards approaching near-optimal MIMO detection performance ONAC-programmable baseband processor.
Proceedings of the IEEE International Conference on Acoustics, 2014

2013
An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11AD standard.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

A processor based multi-standard low-power LDPC engine for multi-Gbps wireless communication.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013

2012
Design, implementation and prototyping of an iterative receiver for bit-interleaved coded modulation system dedicated to DVB-T2.
PhD thesis, 2012

2011
A shuffled iterative bit-interleaved coded modulation receiver for the DVB-T2 standard: Design, implementation and FPGA prototyping.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Efficient iterative receiver for bit-Interleaved Coded Modulation according to the DVB-T2 standard.
Proceedings of the IEEE International Conference on Acoustics, 2011

2009
Design of rotated QAM mapper/demapper for the DVB-T2 standard.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009


  Loading...