Zizheng Dong

Orcid: 0000-0003-4521-1736

According to our database1, Zizheng Dong authored at least 7 papers between 2023 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
A 51.19 mm<sup>2</sup>, 4 TB/s bandwidth 3D Logic-on-SRAM Stacking CGRA Chip.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025
Efficient Die-to-Die Communication: UCIe Link Simulation and Optimization in a Chiplet-Based System.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2025

An Energy-Efficient CPU-FPGA Heterogeneous Acceleration System for Third-Generation Genomic Sequencing Based on Minimap2.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2025

A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip.
IEEE Trans. Very Large Scale Integr. Syst., June, 2025

2024
A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
A $\boldsymbol{4} \times \boldsymbol{112}-\mathbf{Gb}/\mathbf{s}$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged Optics.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

MUG5: Modeling of Universal Chiplet Interconnect Express (UCIe) Standard Based on gem5.
Proceedings of the 15th IEEE International Conference on ASIC, 2023


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