Ankita Nayak

Orcid: 0000-0001-7821-0460

According to our database1, Ankita Nayak authored at least 11 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2024
Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.
IEEE J. Solid State Circuits, March, 2024

2023
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains.
ACM Trans. Reconfigurable Technol. Syst., June, 2023

AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.
ACM Trans. Embed. Comput. Syst., March, 2023

2022
Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022


mflowgen: a modular flow generator and ecosystem for community-driven physical design: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Enabling Reusable Physical Design Flows with Modular Flow Generators.
CoRR, 2021

2020
A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020


Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2018
DNN Dataflow Choice Is Overrated.
CoRR, 2018


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