Kavya Sreedhar

Orcid: 0000-0002-8456-6313

According to our database1, Kavya Sreedhar authored at least 10 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.
IEEE J. Solid State Circuits, March, 2024

2023
AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.
ACM Trans. Embed. Comput. Syst., March, 2023

2022
A Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Enabling and Accelerating Dynamic Vision Transformer Inference for Real-Time Applications.
CoRR, 2022

Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022


2021
Fast Extended GCD Calculation for Large Integers for Verifiable Delay Functions.
IACR Cryptol. ePrint Arch., 2021

Compiling Halide Programs to Push-Memory Accelerators.
CoRR, 2021

Automating System Configuration.
Proceedings of the Formal Methods in Computer Aided Design, 2021

2020


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