Ansh Rupani

Orcid: 0000-0003-2610-197X

According to our database1, Ansh Rupani authored at least 8 papers between 2018 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2022
Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits.
IEEE Trans. Emerg. Top. Comput., 2022

Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy.
IEEE Des. Test, 2022

2021
A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies.
IEEE Access, 2021

END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator.
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021

Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

2019
Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Exploiting Emerging Reconfigurable Technologies for Secure Devices.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018
A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018


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