Christian Mayr

IEEE Trans. Biomed. Circuits Syst., 2022

The operating system of the neuromorphic BrainScaleS-1 system.

[BibT_eX]

[DOI]

Neurocomputing, 2022

Convolutional Neural Networks Quantization with Double-Stage Squeeze-and-Threshold.

[BibT_eX]

[DOI]

Int. J. Neural Syst., 2022

Convolutional Neural Networks Quantization with Attention.

[BibT_eX]

[DOI]

CoRR, 2022

EGRU: Event-based GRU for activity-sparse inference and learning.

[BibT_eX]

[DOI]

Anand Subramoney

Khaleelulla Khan Nazeer

Mark Schöne

David Kappel

CoRR, 2022

How to design an input stage for neural recording system in 22 nm FDSOI.

[BibT_eX]

[DOI]

Sebastian Höppner

Richard Miru George

Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

A Single Battery Supply Power Concept for a Neuro Recording and Flexible Processing Chain in 22 nm.

[BibT_eX]

[DOI]

Stefan Hänzsche

Marc Berthel

Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022

A Random Linear Network Coding Platform MPSoC Designed in 22nm FDSOI.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Improvement of Rejection for AI Safety through Loss-Based Monitoring.

[BibT_eX]

[DOI]

Proceedings of the Workshop on Artificial Intelligence Safety 2022 (AISafety 2022) co-located with the Thirty-First International Joint Conference on Artificial Intelligence and the Twenty-Fifth European Conference on Artificial Intelligence (IJCAI-ECAI-2022), 2022

Hardware-Efficient Ultrasonic Entrance Counting: Comparing Different Machine Learning Approaches.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Pattern Recognition, 2022

Prototyping of Low-Cost Configurable Sparse Neural Processing Unit with Buffer and Mixed-Precision Reshapeable MAC Array.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Parallel and Distributed Systems, 2022

Radar-Based Gesture Recognition with Spiking Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Frontiers of Signal Processing, 2022

Neural Architecture Search for Low-Precision Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2022, 2022

The Scale4Edge RISC-V Ecosystem.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Industry-track: Towards Agile Design of Neural Processing Unit.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2022

Various Distance Metrics Evaluation on Neural Spike Classification.

[BibT_eX]

[DOI]

Shengpeng Guo

Liyuan Guo

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022

ZEN: A flexible energy-efficient hardware classifier exploiting temporal sparsity in ECG data.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

Real-time Radar Gesture Classification with Spiking Neural Network on SpiNNaker 2 Prototype.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

Spiking Neural Network based Real-time Radar Gesture Recognition Live Demonstration.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021

Hardware Implementation of an OPC UA Server for Industrial Field Devices.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Hardware Acceleration of EEG-Based Emotion Classification Systems: A Comprehensive Survey.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2021

Flexible Multi-Channel Analog-Frontend for Ultra-Low Power Environmental Sensing.

[BibT_eX]

[DOI]

IEEE Open J. Circuits Syst., 2021

Comparing Loihi with a SpiNNaker 2 prototype on low-latency keyword spotting and adaptive robotic control.

[BibT_eX]

[DOI]

Neuromorph. Comput. Eng., 2021

Real-time Hardware Implementation of ARM CoreSight Trace Decoder.

[BibT_eX]

[DOI]

Wolfgang H. Krautschneider

IEEE Des. Test, 2021

The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing.

[BibT_eX]

[DOI]

CoRR, 2021

Phase-based Doppler Disambiguation in TDM and BPM MIMO FMCW Radars.

[BibT_eX]

[DOI]

Proceedings of the IEEE Radio and Wireless Symposium, 2021

Low Power CMOS Thyristor-Based Relaxation Oscillator with Efficient Current Compensation.

[BibT_eX]

[DOI]

Marcel Jotschke

Gokulkumar Palanisamy

Torsten Reich

Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021

Ultra-High Compression of Twiddle Factor ROMs in Multi-Core DSP for FMCW Radars.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Opportunities For A Hardware-Based OPC UA Server Implementation In Industry 4.0.

[BibT_eX]

[DOI]

Proceedings of the IECON 2021, 2021

Delay-Based Neural Computation: Pulse Routing Architecture and Benchmark Application in FPGA.

[BibT_eX]

[DOI]

Vasilis N. Thanasoulis

Bernhard Vogginger

Proceedings of the 28th IEEE International Conference on Electronics, 2021

Applied Spiking Neural Networks for Radar-based Gesture Recognition.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Event-Based Control, 2021

Squeeze-and-Threshold Based Quantization for Low-Precision Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 22nd Engineering Applications of Neural Networks Conference, 2021

Analyzing ARM CoreSight ETMv4.x Data Trace Stream with a Real-time Hardware Accelerator.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Ultra-low Power and Area-efficient Hardware Accelerator for Adaptive Neural Signal Compression.

[BibT_eX]

[DOI]

Qier Ma

Liyuan Guo

Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021

2020

Mean Field Approach for Configuring Population Dynamics on a Biohybrid Neuromorphic System.

[BibT_eX]

[DOI]

Massimiliano Giulioni

J. Signal Process. Syst., 2020

Method for the Computer-Aided Schematic Design and Simulation of Hydrogel-Based Microfluidic Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Low-Power Low-Latency Keyword Spotting and Adaptive Control with a SpiNNaker 2 Prototype and Comparison with Loihi.

[BibT_eX]

[DOI]

CoRR, 2020

A 10.5µW programmable SAR ADC Frontend with SC Preamplifier for Low-Power IoT Sensor Nodes.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE World Forum on Internet of Things, 2020

Mapping Deep Neural Networks on SpiNNaker2.

[BibT_eX]

[DOI]

Proceedings of the NICE '20: Neuro-inspired Computational Elements Workshop, 2020

Event-based Neural Network for ECG Classification with Delta Encoding and Early Stopping.

[BibT_eX]

[DOI]

Proceedings of the 6th International Conference on Event-Based Control, 2020

2019

Dynamic Power Management for Neuromorphic Many-Core Systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Efficient Reward-Based Structural Plasticity on a SpiNNaker 2 Prototype.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2019

SpiNNaker 2: A 10 Million Core Processor System for Brain Simulation and Machine Learning.

[BibT_eX]

[DOI]

Sebastian Höppner

Steve B. Furber

CoRR, 2019

Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

A Multi-Bit PFD Architecture for ADPLLs with Built-In Jitter Self-Calibration.

[BibT_eX]

[DOI]

Sebastian Höppner

Alexander Oefelein

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Fast Lock-In Ultra Low-Voltage ADPLL Clock Generator with Adaptive Body Biasing in 22nm FDSOI Technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Application-specific architectures for energy-efficient database query processing and optimization.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

A geographically distributed bio-hybrid neural network with memristive plasticity.

[BibT_eX]

[DOI]

Themistoklis Prodromakis

CoRR, 2017

Neuromorphic Hardware In The Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-Scale System.

[BibT_eX]

[DOI]

CoRR, 2017

Pattern representation and recognition with accelerated analog neuromorphic systems.

[BibT_eX]

[DOI]

CoRR, 2017

Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

Pattern representation and recognition with accelerated analog neuromorphic systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A fixed point exponential function accelerator for a neuromorphic many-core system.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Dynamic voltage and frequency scaling for neuromorphic many-core systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Neuromorphic hardware in the loop: Training a deep spiking network on the BrainScaleS wafer-scale system.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Joint Conference on Neural Networks, 2017

A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

A Calibration Technique for Bang-Bang ADPLLs Using Jitter Distribution Monitoring.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2016

True random number generation from bang-bang ADPLL jitter.

[BibT_eX]

[DOI]

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

A database accelerator for energy-efficient query processing and optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

Beyond spike-timing dependent plasticity in memristor crossbar arrays.

[BibT_eX]

[DOI]

Hesham Mostafa

Giacomo Indiveri

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An MPSoC for energy-efficient database query processing.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Event-based softcore processor in a biohybrid setup applied to structural plasticity.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Event-based Control, 2015

2014

Switched-Capacitor Realization of Presynaptic Short-Term-Plasticity and Stop-Learning Synapses in 28 nm CMOS.

[BibT_eX]

[DOI]

CoRR, 2014

OTA based 200 GΩ resistance on 700 μm2 in 180 nm CMOS for neuromorphic applications.

[BibT_eX]

[DOI]

CoRR, 2014

VLSI implementation of a conductance-based multi-synapse using switched-capacitor circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Live demonstration: Multiple-timescale plasticity in a neuromorphic system.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A model based comparison of BiFeO3 device applicability in neuromorphic hardware.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A location-independent direct link neuromorphic interface.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

Live demonstration: Ethernet communication linking two large-scale neuromorphic systems.

[BibT_eX]

[DOI]

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012

A 32 GBit/s communication SoC for a waferscale neuromorphic system.

[BibT_eX]

[DOI]

Integr., 2012

Waveform Driven Plasticity in BiFeO3 Memristive Devices: Model and Implementation.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 25: 26th Annual Conference on Neural Information Processing Systems 2012. Proceedings of a meeting held December 3-6, 2012

Live demonstration: A scaled-down version of the BrainScaleS wafer-scale neuromorphic system.

[BibT_eX]

[DOI]

Marc-Olivier Schwartz

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Long-term pulse stimulation and recording in an accelerated neuromorphic system.

[BibT_eX]

[DOI]

Vasilis N. Thanasoulis

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Dedicated FPGA communication architecture and design for a large-scale neuromorphic system.

[BibT_eX]

[DOI]

Vasilis N. Thanasoulis

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems.

[BibT_eX]

[DOI]

Biol. Cybern., 2011

Live demonstration: Packet-based AER with 3Gevent/s cumulative throughput.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Synapse dynamics in CMOS derived from a model of neurotransmitter release.

[BibT_eX]

[DOI]

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

Replicating experimental spike and rate based neural learning in CMOS.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Highly integrated packet-based AER communication infrastructure with 3Gevent/S throughput.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

A critique of BCM behavior verification for STDP-type plasticity models.

[BibT_eX]

[DOI]

Proceedings of the 18th European Symposium on Artificial Neural Networks, 2010

2009

A novel ADPLL design using successive approximation frequency control.

[BibT_eX]

[DOI]

Microelectron. J., 2009

Transient responses of activity-dependent synapses to modulated pulse trains.

[BibT_eX]

[DOI]

Neurocomputing, 2009

On the Relation between Bursts and Dynamic Synapse Properties: A Modulation-Based Ansatz.

[BibT_eX]

[DOI]

Comput. Intell. Neurosci., 2009

Current conveyor based amplifier and adaptive buffer for use in an analog frontend.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

Untersuchungen zur Implementierung von Bildverarbeitungsalgorithmen mittels pulsgekoppelter neuronaler Netze.

[BibT_eX]

[DOI]

PhD thesis, 2008

BCM and Membrane Potential: Alternative Ways to Timing Dependent Plasticity.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neuro-Information Processing, 15th International Conference, 2008

2007

Gabor-Like Image Filtering Using a Neural Microcircuit.

[BibT_eX]

[DOI]

Arne Heittmann

IEEE Trans. Neural Networks, 2007

Nearest Neighborhood Grayscale Operator for Hardware-Efficient Microscale Texture Extraction.

[BibT_eX]

[DOI]

Andreas König

EURASIP J. Adv. Signal Process., 2007

Neighborhood Rank Order Coding for Robust Texture Analysis and Feature Extraction.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Hybrid Intelligent Systems, 2007

2005

Applying Spiking Neural Nets to Noise Shaping.

[BibT_eX]

[DOI]