Satwik Patnaik
Orcid: 0000-0002-8975-2414
According to our database1,
Satwik Patnaik
authored at least 56 papers
between 2017 and 2024.
Collaborative distances:
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Bibliography
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024
CoRR, 2024
2023
VIGILANT: Vulnerability Detection Tool Against Fault-Injection Attacks for Locking Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
$\tt{PoisonedGNN}$: Backdoor Attack on Graph Neural Networks-Based Hardware Security Systems.
IEEE Trans. Computers, October, 2023
IEEE Trans. Neural Networks Learn. Syst., September, 2023
Titan: Security Analysis of Large-Scale Hardware Obfuscation Using Graph Neural Networks.
IEEE Trans. Inf. Forensics Secur., 2023
IEEE Trans. Emerg. Top. Comput., 2023
Securing Cloud FPGAs Against Power Side-Channel Attacks: A Case Study on Iterative AES.
CoRR, 2023
PoisonedGNN: Backdoor Attack on Graph Neural Networks-based Hardware Security Systems.
CoRR, 2023
UN-SPLIT: Attacking Split Manufacturing Using Link Prediction in Graph Neural Networks.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2023
ExploreFault: Identifying Exploitable Fault Models in Block Ciphers with Reinforcement Learning.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
Hide and Seek: Seeking the (Un)-Hidden Key in Provably-Secure Logic Locking Techniques.
IEEE Trans. Inf. Forensics Secur., 2022
Valkyrie: Vulnerability Assessment Tool and Attack for Provably-Secure Logic Locking Techniques.
IEEE Trans. Inf. Forensics Secur., 2022
Opening the Doors to Dynamic Camouflaging: Harnessing the Power of Polymorphic Devices.
IEEE Trans. Emerg. Top. Comput., 2022
Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits.
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Emerg. Top. Comput., 2022
GNNUnlock+: A Systematic Methodology for Designing Graph Neural Networks-Based Oracle-Less Unlocking Schemes for Provably Secure Logic Locking.
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology.
Integr., 2022
IACR Cryptol. ePrint Arch., 2022
Hide & Seek: Seeking the (Un)-Hidden key in Provably-Secure Logic Locking Techniques.
CoRR, 2022
SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Reinforcement Learning for Hardware Security: Opportunities, Developments, and Challenges.
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
MuxLink: Circumventing Learning-Resilient MUX-Locking Using Graph Neural Network-based Link Prediction.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
ATTRITION: Attacking Static Hardware Trojan Detection Techniques Using Reinforcement Learning.
Proceedings of the 2022 ACM SIGSAC Conference on Computer and Communications Security, 2022
2021
IEEE Trans. Inf. Forensics Secur., 2021
IEEE Trans. Inf. Forensics Secur., 2021
A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects.
IEEE Trans. Emerg. Top. Comput., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic Locking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Computers, 2020
Ensemble-learning based neural networks for novelty detection in multi-class systems.
Appl. Soft Comput., 2020
SMART: A Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory.
IEEE Access, 2020
2019
IEEE Des. Test, 2019
Toward Physically Unclonable Functions from Plasmonics-Enhanced Silicon Disc Resonators.
CoRR, 2019
An Interposer-Based Root of Trust: Seize the Opportunity for Secure System-Level Integration of Untrusted Chiplets.
CoRR, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the International Conference on Omni-Layer Intelligent Systems, 2019
2018
Best of both worlds: integration of split manufacturing and camouflaging into a security-driven CAD flow for 3D ICs.
Proceedings of the International Conference on Computer-Aided Design, 2018
Advancing hardware security using polymorphic and stochastic spin-hall effect devices.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Raise your game for split manufacturing: restoring the true functionality through BEOL.
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
Proceedings of the 2017 IEEE Wireless Communications and Networking Conference, 2017
Rethinking split manufacturing: An information-theoretic approach with secure layout techniques.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017